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authorRajendra Nayak <rnayak@ti.com>2009-06-09 19:00:41 +0200
committerKevin Hilman <khilman@deeprootsystems.com>2009-11-11 23:42:28 +0100
commitf265dc4c5d39f2bd369d97c87a7bd89061b159d4 (patch)
treedb16053ad7010c141a054ab0c8b5c243c311962f /arch/arm/mach-omap2/control.c
parentOMAP3: PM: Enable IO-CHAIN wakeup (diff)
downloadlinux-f265dc4c5d39f2bd369d97c87a7bd89061b159d4.tar.xz
linux-f265dc4c5d39f2bd369d97c87a7bd89061b159d4.zip
OMAP3: PM: Program SDRC to send self refresh on timeout of AUTO_CNT
Due to an OMAP3 errata (1.142), on HS/EMU devices SDRC should be programed to issue automatic self refresh on timeout of AUTO_CNT = 1 prior to any transition to OFF mode. This is needed only on sil rev's ES3.0 and above. This patch enables the above needed WA in the SDRC power register value stored in scratchpad, so that ROM code restores this value in SDRC POWER on the wakeup path. The original SDRC POWER register value is stored and restored back in omap_sram_idle() function. This fixes some random crashes observed while stressing suspend on HS/EMU devices. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/control.c')
-rw-r--r--arch/arm/mach-omap2/control.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 2ff8d7cc60a2..cdd1f35636dd 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -265,7 +265,21 @@ void omap3_save_scratchpad_contents(void)
(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
sdrc_block_contents.dll_b_ctrl = 0x0;
- sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
+ /*
+ * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
+ * be programed to issue automatic self refresh on timeout
+ * of AUTO_CNT = 1 prior to any transition to OFF mode.
+ */
+ if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
+ && (omap_rev() >= OMAP3430_REV_ES3_0))
+ sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
+ ~(SDRC_POWER_AUTOCOUNT_MASK|
+ SDRC_POWER_CLKCTRL_MASK)) |
+ (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
+ SDRC_SELF_REFRESH_ON_AUTOCOUNT;
+ else
+ sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
+
sdrc_block_contents.cs_0 = 0x0;
sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);