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| author | Tony Lindgren <tony@atomide.com> | 2014-07-29 13:03:30 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-07-29 13:03:30 +0200 |
| commit | d40dbcd57b942528d7dbd17ace0b32136d848ecb (patch) | |
| tree | 2a37983629948ff3086ad1d13d6d1612afa8478a /arch/arm/mach-omap2/dpll3xxx.c | |
| parent | Merge branch 'omap-for-v3.17/mailbox' into omap-for-v3.17/soc (diff) | |
| parent | ARM: OMAP2+: clock: allow omap2_dpll_round_rate() to round to next-lowest rate (diff) | |
| download | linux-d40dbcd57b942528d7dbd17ace0b32136d848ecb.tar.xz linux-d40dbcd57b942528d7dbd17ace0b32136d848ecb.zip | |
Merge tag 'for-v3.17/omap-clock-b' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.17/soc
Modify OMAP PLL rate rounding function to round to the exact rate requested
or the next one below it. This is intended to resolve some DSS problems.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/clock-b-v3.17/20140725061121/
Diffstat (limited to 'arch/arm/mach-omap2/dpll3xxx.c')
| -rw-r--r-- | arch/arm/mach-omap2/dpll3xxx.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index cd5f3a0b97bd..ac3d789ac3cd 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -475,6 +475,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct clk *new_parent = NULL; + unsigned long rrate; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -502,8 +503,16 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __clk_prepare(dd->clk_ref); clk_enable(dd->clk_ref); - if (dd->last_rounded_rate != rate) - rate = __clk_round_rate(hw->clk, rate); + /* XXX this check is probably pointless in the CCF context */ + if (dd->last_rounded_rate != rate) { + rrate = __clk_round_rate(hw->clk, rate); + if (rrate != rate) { + pr_warn("%s: %s: final rate %lu does not match desired rate %lu\n", + __func__, __clk_get_name(hw->clk), + rrate, rate); + rate = rrate; + } + } if (dd->last_rounded_rate == 0) return -EINVAL; |