diff options
| author | Paul Walmsley <paul@pwsan.com> | 2012-04-19 12:04:38 +0200 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-04-19 12:25:08 +0200 |
| commit | 3af35fbcd088e0b675fa423a879c596384894180 (patch) | |
| tree | 3d408953bfe26218081879b0ef0ca0e89570b439 /arch/arm/mach-omap2/omap_hwmod_2420_data.c | |
| parent | ARM: OMAP3: hwmod data: add IVA hard reset lines, main clock, clockdomain (diff) | |
| download | linux-3af35fbcd088e0b675fa423a879c596384894180.tar.xz linux-3af35fbcd088e0b675fa423a879c596384894180.zip | |
ARM: OMAP2xxx: hwmod data: start to fix the IVA1, IVA2 and DSP
N800 logs this message on boot:
[ 0.182281] omap_hwmod: iva: cannot be enabled for reset (3)
Fix by creating basic IVA1 and DSP hwmods for OMAP2420, and a basic IVA2
hwmod for OMAP2430. There is still more information to be added, but
this should resolve the immediate issue.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_2420_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_2420_data.c | 46 |
1 files changed, 43 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index b01b66a85f2e..2c087ffc6a92 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -43,10 +43,41 @@ * IP blocks */ -/* IVA2 (IVA2) */ +/* IVA1 (IVA1) */ +static struct omap_hwmod_class iva1_hwmod_class = { + .name = "iva1", +}; + +static struct omap_hwmod_rst_info omap2420_iva_resets[] = { + { .name = "iva", .rst_shift = 8 }, +}; + static struct omap_hwmod omap2420_iva_hwmod = { .name = "iva", - .class = &iva_hwmod_class, + .class = &iva1_hwmod_class, + .clkdm_name = "iva1_clkdm", + .rst_lines = omap2420_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), + .main_clk = "iva1_ifck", +}; + +/* DSP */ +static struct omap_hwmod_class dsp_hwmod_class = { + .name = "dsp", +}; + +static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "mmu", .rst_shift = 1 }, +}; + +static struct omap_hwmod omap2420_dsp_hwmod = { + .name = "dsp", + .class = &dsp_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap2420_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), + .main_clk = "dsp_fck", }; /* I2C common */ @@ -234,7 +265,15 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { static struct omap_hwmod_ocp_if omap2420_l3__iva = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2420_iva_hwmod, - .clk = "iva1_ifck", + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* DSP <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__dsp = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2420_dsp_hwmod, + .clk = "dsp_ick", .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -402,6 +441,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__i2c1, &omap2420_l4_core__i2c2, &omap2420_l3__iva, + &omap2420_l3__dsp, &omap2420_l4_wkup__timer1, &omap2xxx_l4_core__timer2, &omap2xxx_l4_core__timer3, |