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| author | Thara Gopinath <thara@ti.com> | 2009-12-09 00:33:15 +0100 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-12-12 01:00:42 +0100 |
| commit | 3863c74b512c1afd3ce6b2f81d8dea9f1d860968 (patch) | |
| tree | 1d7d15664c0ae3a71be7949e9c52ca2f79a73811 /arch/arm/mach-omap2/powerdomains34xx.h | |
| parent | OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behin... (diff) | |
| download | linux-3863c74b512c1afd3ce6b2f81d8dea9f1d860968.tar.xz linux-3863c74b512c1afd3ce6b2f81d8dea9f1d860968.zip | |
OMAP3: PM: Fix for MPU power domain MEM BANK position
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomains34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/powerdomains34xx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index fd09b0827df0..588f7e07d0ea 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h @@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = { .wkdep_srcs = mpu_34xx_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_MPU_QUIRK, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, |