diff options
| author | Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> | 2009-01-16 17:53:48 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-11-11 23:42:27 +0100 |
| commit | 89139dce8a0060d97a46cebde570a8f55c314712 (patch) | |
| tree | 9490675c8f1f88c1ab37248082cb1c2e2230091e /arch/arm/mach-omap2/sleep34xx.S | |
| parent | PM: Disable usb host HW save and restore (diff) | |
| download | linux-89139dce8a0060d97a46cebde570a8f55c314712.tar.xz linux-89139dce8a0060d97a46cebde570a8f55c314712.zip | |
OMAP3: PM: Wait for SDRC ready iso a blind delay
This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/sleep34xx.S')
| -rw-r--r-- | arch/arm/mach-omap2/sleep34xx.S | 48 |
1 files changed, 36 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index dedfa0e6c639..15268f8b61de 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -29,6 +29,7 @@ #include <mach/io.h> #include <plat/control.h> +#include "cm.h" #include "prm.h" #include "sdrc.h" @@ -38,6 +39,7 @@ #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ OMAP3430_PM_PREPWSTST) #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL +#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) #define SRAM_BASE_P 0x40200000 #define CONTROL_STAT 0x480022F0 #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is @@ -52,6 +54,8 @@ #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) +#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) +#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) .text /* Function call to get the restore pointer for resume from OFF */ @@ -187,7 +191,7 @@ loop: nop nop nop - bl i_dll_wait + bl wait_sdrc_ok ldmfd sp!, {r0-r12, pc} @ restore regs and return restore_es3: @@ -539,21 +543,41 @@ skip_l2_inval: nop nop nop - bl i_dll_wait + bl wait_sdrc_ok /* restore regs and return */ ldmfd sp!, {r0-r12, pc} -i_dll_wait: - ldr r4, clk_stabilize_delay +/* Make sure SDRC accesses are ok */ +wait_sdrc_ok: + ldr r4, cm_idlest1_core + ldr r5, [r4] + and r5, r5, #0x2 + cmp r5, #0 + bne wait_sdrc_ok + ldr r4, sdrc_power + ldr r5, [r4] + bic r5, r5, #0x40 + str r5, [r4] +wait_dll_lock: + /* Is dll in lock mode? */ + ldr r4, sdrc_dlla_ctrl + ldr r5, [r4] + tst r5, #0x4 + bxne lr + /* wait till dll locks */ + ldr r4, sdrc_dlla_status + ldr r5, [r4] + and r5, r5, #0x4 + cmp r5, #0x4 + bne wait_dll_lock + bx lr -i_dll_delay: - subs r4, r4, #0x1 - bne i_dll_delay - ldr r4, sdrc_power - ldr r5, [r4] - bic r5, r5, #0x40 - str r5, [r4] - bx lr +cm_idlest1_core: + .word CM_IDLEST1_CORE_V +sdrc_dlla_status: + .word SDRC_DLLA_STATUS_V +sdrc_dlla_ctrl: + .word SDRC_DLLA_CTRL_V pm_prepwstst_core: .word PM_PREPWSTST_CORE_V pm_prepwstst_core_p: |