diff options
| author | Joel Fernandes <joelf@ti.com> | 2014-04-30 04:53:47 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-05-06 02:32:25 +0200 |
| commit | 55fde31cae6a815a184271317abf15f468abcb44 (patch) | |
| tree | 0c490e96403b97f2c7b00b9afcec84f31715eb18 /arch/arm/mach-omap2 | |
| parent | ARM: dts: AM3517: Disable absent IPs inherited from OMAP3 (diff) | |
| download | linux-55fde31cae6a815a184271317abf15f468abcb44.tar.xz linux-55fde31cae6a815a184271317abf15f468abcb44.zip | |
ARM: OMAP5: Redo THUMB mode switch on secondary CPU
Here's a redo of the patch [1] that effectively does the same
thing but is the right way to do things by using ENDPROC instead.
The firmware correctly switches to THUMB before entry.
The patch applies ontop of the earlier patch [1].
[1] https://lkml.org/lkml/2014/4/22/1044
Suggested-by: Dave Martin <Dave.Martin@arm.com>
Cc: Dave Martin <Dave.Martin@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/omap-headsmp.S | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 40c5d5f1451c..4993d4bfe9b2 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -31,10 +31,6 @@ * register AuxCoreBoot0. */ ENTRY(omap5_secondary_startup) -.arm -THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode. -THUMB( bx r9 ) @ If this is a Thumb-2 kernel, -THUMB( .thumb ) @ switch to Thumb now. wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] mov r0, r0, lsr #5 @@ -43,7 +39,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 cmp r0, r4 bne wait b secondary_startup -END(omap5_secondary_startup) +ENDPROC(omap5_secondary_startup) /* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which |