diff options
| author | Jiri Kosina <jkosina@suse.cz> | 2014-11-20 14:42:02 +0100 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2014-11-20 14:42:02 +0100 |
| commit | a02001086bbfb4da35d1228bebc2f1b442db455f (patch) | |
| tree | 62ab47936cef06fd08657ca5b6cd1df98c19be57 /arch/arm/mach-omap2 | |
| parent | kernel: trace: fix printk message (diff) | |
| parent | Linux 3.18-rc5 (diff) | |
| download | linux-a02001086bbfb4da35d1228bebc2f1b442db455f.tar.xz linux-a02001086bbfb4da35d1228bebc2f1b442db455f.zip | |
Merge Linus' tree to be be to apply submitted patches to newer code than
current trivial.git base
Diffstat (limited to 'arch/arm/mach-omap2')
100 files changed, 1949 insertions, 7388 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index e7189dcc9309..f4d06aea8460 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -1,9 +1,6 @@ menu "TI OMAP/AM/DM/DRA Family" depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 -config ARCH_OMAP - bool - config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_MULTI_V6 @@ -25,7 +22,6 @@ config ARCH_OMAP4 bool "TI OMAP4" depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS - select ARCH_HAS_OPP select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_CPU_SUSPEND if PM select ARM_ERRATA_720789 @@ -44,7 +40,6 @@ config SOC_OMAP5 bool "TI OMAP5" depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS - select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM select ARM_GIC select HAVE_ARM_SCU if SMP @@ -56,14 +51,12 @@ config SOC_AM33XX bool "TI AM33XX" depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS - select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM config SOC_AM43XX bool "TI AM43x" depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS - select ARCH_HAS_OPP select ARM_GIC select MACH_OMAP_GENERIC select MIGHT_HAVE_CACHE_L2X0 @@ -72,7 +65,6 @@ config SOC_DRA7XX bool "TI DRA7XX" depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS - select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM select ARM_GIC select HAVE_ARM_ARCH_TIMER @@ -91,6 +83,7 @@ config ARCH_OMAP2PLUS select PINCTRL select SOC_BUS select TI_PRIV_EDMA + select OMAP_IRQCHIP help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fa7800015753..d9e94122073e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -10,7 +10,6 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \ common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ omap_device.o sram.o drm.o -omap-2-3-common = irq.o hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ omap_hwmod_common_data.o clock-common = clock.o clock_common_data.o \ @@ -20,7 +19,7 @@ secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) +obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) @@ -87,9 +86,10 @@ ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o -obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o -obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o +omap-4-5-pm-common = pm44xx.o omap-mpuss-lowpower.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common) +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common) +obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common) obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o @@ -102,7 +102,10 @@ endif ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o +omap-4-5-idle-common = cpuidle44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-idle-common) +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-idle-common) +obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-idle-common) endif # PRCM @@ -176,13 +179,11 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o -obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o -obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o +obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o @@ -202,6 +203,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data +obj-y += omap_hwmod_common_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index d95d0ef1354a..d21a3048d06b 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -625,7 +625,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap_3430sdp_init, .init_late = omap3430_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 0d499a1878f6..212c3160de18 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -142,7 +142,6 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") .map_io = omap3_map_io, .init_early = am35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = am3517_crane_init, .init_late = am35xx_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 4f9383cecf76..1c091b3fa312 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -366,7 +366,6 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .map_io = omap3_map_io, .init_early = am35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = am3517_evm_init, .init_late = am35xx_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 018353d88b96..c6df8eec4553 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -766,7 +766,6 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t35_init, .init_late = omap35xx_init_late, .init_time = omap3_sync32k_timer_init, @@ -779,7 +778,6 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730") .map_io = omap3_map_io, .init_early = omap3630_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3730_init, .init_late = omap3630_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 4eb5e6f2f7f5..8a2c1677964c 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -329,7 +329,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") .map_io = omap3_map_io, .init_early = am35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3517_init, .init_late = am35xx_init_late, .init_time = omap3_gptimer_timer_init, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index cdc4fb9960a9..d8e4f346936a 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -647,7 +647,6 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = devkit8000_init, .init_late = omap35xx_init_late, .init_time = omap3_secure_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index e87f2a83d6bf..2d245c2e641c 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, board_nand_data.nr_parts = nr_parts; board_nand_data.devsize = nand_type; - board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW; + board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW; gpmc_nand_init(&board_nand_data, gpmc_t); } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 9480997ba616..608079a1aba6 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -27,7 +27,7 @@ #define gic_of_init NULL #endif -static struct of_device_id omap_dt_match_table[] __initdata = { +static const struct of_device_id omap_dt_match_table[] __initconst = { { .compatible = "simple-bus", }, { .compatible = "ti,omap-infra", }, { } @@ -43,7 +43,7 @@ static void __init omap_generic_init(void) } #ifdef CONFIG_SOC_OMAP2420 -static const char *omap242x_boards_compat[] __initconst = { +static const char *const omap242x_boards_compat[] __initconst = { "ti,omap2420", NULL, }; @@ -52,8 +52,6 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") .reserve = omap_reserve, .map_io = omap242x_map_io, .init_early = omap2420_init_early, - .init_irq = omap_intc_of_init, - .handle_irq = omap2_intc_handle_irq, .init_machine = omap_generic_init, .init_time = omap2_sync32k_timer_init, .dt_compat = omap242x_boards_compat, @@ -62,7 +60,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP2430 -static const char *omap243x_boards_compat[] __initconst = { +static const char *const omap243x_boards_compat[] __initconst = { "ti,omap2430", NULL, }; @@ -71,8 +69,6 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") .reserve = omap_reserve, .map_io = omap243x_map_io, .init_early = omap2430_init_early, - .init_irq = omap_intc_of_init, - .handle_irq = omap2_intc_handle_irq, .init_machine = omap_generic_init, .init_time = omap2_sync32k_timer_init, .dt_compat = omap243x_boards_compat, @@ -81,7 +77,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP3 -static const char *omap3_boards_compat[] __initconst = { +static const char *const omap3_boards_compat[] __initconst = { "ti,omap3430", "ti,omap3", NULL, @@ -91,8 +87,6 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .reserve = omap_reserve, .map_io = omap3_map_io, .init_early = omap3430_init_early, - .init_irq = omap_intc_of_init, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, .init_late = omap3_init_late, .init_time = omap3_sync32k_timer_init, @@ -100,7 +94,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap36xx_boards_compat[] __initconst = { +static const char *const omap36xx_boards_compat[] __initconst = { "ti,omap36xx", NULL, }; @@ -109,8 +103,6 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)") .reserve = omap_reserve, .map_io = omap3_map_io, .init_early = omap3630_init_early, - .init_irq = omap_intc_of_init, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, .init_late = omap3_init_late, .init_time = omap3_sync32k_timer_init, @@ -118,7 +110,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap3_gp_boards_compat[] __initconst = { +static const char *const omap3_gp_boards_compat[] __initconst = { "ti,omap3-beagle", "timll,omap3-devkit8000", NULL, @@ -128,8 +120,6 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .reserve = omap_reserve, .map_io = omap3_map_io, .init_early = omap3430_init_early, - .init_irq = omap_intc_of_init, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, .init_late = omap3_init_late, .init_time = omap3_secure_sync32k_timer_init, @@ -137,7 +127,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *am3517_boards_compat[] __initconst = { +static const char *const am3517_boards_compat[] __initconst = { "ti,am3517", NULL, }; @@ -146,8 +136,6 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)") .reserve = omap_reserve, .map_io = omap3_map_io, .init_early = am35xx_init_early, - .init_irq = omap_intc_of_init, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, .init_late = omap3_init_late, .init_time = omap3_gptimer_timer_init, @@ -157,7 +145,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM33XX -static const char *am33xx_boards_compat[] __initconst = { +static const char *const am33xx_boards_compat[] __initconst = { "ti,am33xx", NULL, }; @@ -166,8 +154,6 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") .reserve = omap_reserve, .map_io = am33xx_map_io, .init_early = am33xx_init_early, - .init_irq = omap_intc_of_init, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, .init_late = am33xx_init_late, .init_time = omap3_gptimer_timer_init, @@ -177,7 +163,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP4 -static const char *omap4_boards_compat[] __initconst = { +static const char *const omap4_boards_compat[] __initconst = { "ti,omap4460", "ti,omap4430", "ti,omap4", @@ -199,7 +185,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP5 -static const char *omap5_boards_compat[] __initconst = { +static const char *const omap5_boards_compat[] __initconst = { "ti,omap5432", "ti,omap5430", "ti,omap5", @@ -221,7 +207,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM43XX -static const char *am43_boards_compat[] __initconst = { +static const char *const am43_boards_compat[] __initconst = { "ti,am4372", "ti,am43", NULL, @@ -240,7 +226,9 @@ MACHINE_END #endif #ifdef CONFIG_SOC_DRA7XX -static const char *dra74x_boards_compat[] __initconst = { +static const char *const dra74x_boards_compat[] __initconst = { + "ti,am5728", + "ti,am5726", "ti,dra742", "ti,dra7", NULL, @@ -259,7 +247,9 @@ DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") .restart = omap44xx_restart, MACHINE_END -static const char *dra72x_boards_compat[] __initconst = { +static const char *const dra72x_boards_compat[] __initconst = { + "ti,am5718", + "ti,am5716", "ti,dra722", NULL, }; diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 44a59c3abfb0..c2975af4cd5d 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -422,7 +422,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap_ldp_init, .init_late = omap3430_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index aead77a4bc6d..97767a27ca9d 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -33,6 +33,7 @@ #include "mmc.h" #include "soc.h" #include "gpmc-onenand.h" +#include "common-board-devices.h" #define TUSB6010_ASYNC_CS 1 #define TUSB6010_SYNC_CS 4 @@ -568,29 +569,14 @@ static int n8x0_menelaus_late_init(struct device *dev) } #endif -static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { +struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { .late_init = n8x0_menelaus_late_init, }; -static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { - { - I2C_BOARD_INFO("menelaus", 0x72), - .irq = 7 + OMAP_INTC_START, - .platform_data = &n8x0_menelaus_platform_data, - }, -}; - -static struct aic3x_pdata n810_aic33_data __initdata = { +struct aic3x_pdata n810_aic33_data __initdata = { .gpio_reset = 118, }; -static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - .platform_data = &n810_aic33_data, - }, -}; - static int __init n8x0_late_initcall(void) { if (!board_caps) @@ -612,11 +598,5 @@ void * __init n8x0_legacy_init(void) board_check_revision(); spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); - i2c_register_board_info(0, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); - if (board_is_n810()) - i2c_register_board_info(1, n810_i2c_board_info_2, - ARRAY_SIZE(n810_i2c_board_info_2)); - return &mmc1_data; } diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index e2e52031f056..81de1c68b360 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -588,7 +588,6 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") .map_io = omap3_map_io, .init_early = omap3_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_beagle_init, .init_late = omap3_init_late, .init_time = omap3_secure_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index bab51e64c4b5..6049f60a8813 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -230,7 +230,6 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap3logic_init, .init_late = omap35xx_init_late, .init_time = omap3_sync32k_timer_init, @@ -243,7 +242,6 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap3logic_init, .init_late = omap35xx_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index cf18340eb3bb..f32201656cf3 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -624,7 +624,6 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap3pandora_init, .init_late = omap35xx_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index a2e035e0792a..6311f4b1ee44 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -426,7 +426,6 @@ MACHINE_START(SBC3530, "OMAP3 STALKER") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_stalker_init, .init_late = omap35xx_init_late, .init_time = omap3_secure_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 7da48bc42bbf..a01993e5500f 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -336,7 +336,7 @@ static int __init early_touchbook_revision(char *p) if (!p) return 0; - return strict_strtoul(p, 10, &touchbook_revision); + return kstrtoul(p, 10, &touchbook_revision); } early_param("tbr", early_touchbook_revision); @@ -388,7 +388,6 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_touchbook_init, .init_late = omap3430_init_late, .init_time = omap3_secure_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index f6d384111911..2dae6ccd39bb 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -564,7 +564,6 @@ MACHINE_START(OVERO, "Gumstix Overo") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = overo_init, .init_late = omap35xx_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index db168c9627a1..2d1e5a6beb85 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -134,7 +134,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = rx51_init, .init_late = omap3430_init_late, .init_time = omap3_sync32k_timer_init, diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c deleted file mode 100644 index 3662f4d4c8ea..000000000000 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ /dev/null @@ -1,1931 +0,0 @@ -/* - * OMAP2420 clock data - * - * Copyright (C) 2005-2012 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/clk-private.h> -#include <linux/list.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx.h" -#include "prm2xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR - -/* - * 2420 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); - -DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); - -static struct clk osc_ck; - -static const struct clk_ops osc_ck_ops = { - .recalc_rate = &omap2_osc_clk_recalc, -}; - -static struct clk_hw_omap osc_ck_hw = { - .hw = { - .clk = &osc_ck, - }, -}; - -static struct clk osc_ck = { - .name = "osc_ck", - .ops = &osc_ck_ops, - .hw = &osc_ck_hw.hw, - .flags = CLK_IS_ROOT, -}; - -DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -static struct clk sys_ck; - -static const char *sys_ck_parent_names[] = { - "osc_ck", -}; - -static const struct clk_ops sys_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2xxx_sys_clk_recalc, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -static struct clk dpll_ck; - -static const char *dpll_ck_parent_names[] = { - "sys_ck", -}; - -static const struct clk_ops dpll_ck_ops = { - .init = &omap2_init_clk_clkdm, - .get_parent = &omap2_init_dpll_parent, - .recalc_rate = &omap2_dpllcore_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk_hw_omap dpll_ck_hw = { - .hw = { - .clk = &dpll_ck, - }, - .ops = &clkhwops_omap2xxx_dpll, - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); - -static struct clk core_ck; - -static const char *core_ck_parent_names[] = { - "dpll_ck", -}; - -static const struct clk_ops core_ck_ops = { - .init = &omap2_init_clk_clkdm, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); - -DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk aes_ick; - -static const char *aes_ick_parent_names[] = { - "l4_ck", -}; - -static const struct clk_ops aes_ick_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap aes_ick_hw = { - .hw = { - .clk = &aes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk apll54_ck; - -static const struct clk_ops apll54_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll54_enable, - .disable = &omap2_clk_apll54_disable, - .recalc_rate = &omap2_clk_apll54_recalc, -}; - -static struct clk_hw_omap apll54_ck_hw = { - .hw = { - .clk = &apll54_ck, - }, - .ops = &clkhwops_apll54, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); - -static struct clk apll96_ck; - -static const struct clk_ops apll96_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll96_enable, - .disable = &omap2_clk_apll96_disable, - .recalc_rate = &omap2_clk_apll96_recalc, -}; - -static struct clk_hw_omap apll96_ck_hw = { - .hw = { - .clk = &apll96_ck, - }, - .ops = &clkhwops_apll96, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); - -static struct clk func_96m_ck; - -static const char *func_96m_ck_parent_names[] = { - "apll96_ck", -}; - -DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); - -static struct clk cam_fck; - -static const char *cam_fck_parent_names[] = { - "func_96m_ck", -}; - -static struct clk_hw_omap cam_fck_hw = { - .hw = { - .clk = &cam_fck, - }, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk cam_ick; - -static struct clk_hw_omap cam_ick_hw = { - .hw = { - .clk = &cam_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk des_ick; - -static struct clk_hw_omap des_ick_hw = { - .hw = { - .clk = &des_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dsp_fck_parent_names[] = { - "core_ck", -}; - -static const struct clk_ops dsp_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL }, -}; - -static const char *dsp_ick_parent_names[] = { - "dsp_fck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_IF_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), - OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait, - dsp_ick_parent_names, dsp_fck_ops); - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dss1_fck_parent_names[] = { - "sys_ck", "core_ck", -}; - -static struct clk dss1_fck; - -static const struct clk_ops dss1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS1_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS1_SHIFT, NULL, - dss1_fck_parent_names, dss1_fck_ops); - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL }, -}; - -static const char *func_48m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -static struct clk func_48m_ck; - -static const struct clk_ops func_48m_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static struct clk_hw_omap func_48m_ck_hw = { - .hw = { - .clk = &func_48m_ck, - }, - .clksel = func_48m_clksel, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL }, -}; - -static const char *dss2_fck_parent_names[] = { - "sys_ck", "func_48m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS2_SHIFT, NULL, - dss2_fck_parent_names, dss1_fck_ops); - -static const char *func_54m_ck_parent_names[] = { - "apll54_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, - 0x0, NULL); - -static struct clk dss_54m_fck; - -static const char *dss_54m_fck_parent_names[] = { - "func_54m_ck", -}; - -static struct clk_hw_omap dss_54m_fck_hw = { - .hw = { - .clk = &dss_54m_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); - -static struct clk dss_ick; - -static struct clk_hw_omap dss_ick_hw = { - .hw = { - .clk = &dss_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk eac_fck; - -static struct clk_hw_omap eac_fck_hw = { - .hw = { - .clk = &eac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk eac_ick; - -static struct clk_hw_omap eac_ick_hw = { - .hw = { - .clk = &eac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk emul_ck; - -static struct clk_hw_omap emul_ck_hw = { - .hw = { - .clk = &emul_ck, - }, - .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); - -static struct clk fac_fck; - -static const char *fac_fck_parent_names[] = { - "func_12m_ck", -}; - -static struct clk_hw_omap fac_fck_hw = { - .hw = { - .clk = &fac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk fac_ick; - -static struct clk_hw_omap fac_ick_hw = { - .hw = { - .clk = &fac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static const char *gfx_2d_fck_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -static struct clk gfx_ick; - -static const char *gfx_ick_parent_names[] = { - "core_l3_ck", -}; - -static struct clk_hw_omap gfx_ick_hw = { - .hw = { - .clk = &gfx_ick, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .clkdm_name = "gfx_clkdm", -}; - -DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk gpios_fck; - -static const char *gpios_fck_parent_names[] = { - "func_32k_ck", -}; - -static struct clk_hw_omap gpios_fck_hw = { - .hw = { - .clk = &gpios_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk gpios_ick; - -static const char *gpios_ick_parent_names[] = { - "sys_ck", -}; - -static struct clk_hw_omap gpios_ick_hw = { - .hw = { - .clk = &gpios_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk gpmc_fck; - -static struct clk_hw_omap gpmc_fck_hw = { - .hw = { - .clk = &gpmc_fck, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); - -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static const char *gpt10_fck_parent_names[] = { - "func_32k_ck", "sys_ck", "alt_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT10_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt10_ick; - -static struct clk_hw_omap gpt10_ick_hw = { - .hw = { - .clk = &gpt10_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT11_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt11_ick; - -static struct clk_hw_omap gpt11_ick_hw = { - .hw = { - .clk = &gpt11_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT12_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt12_ick; - -static struct clk_hw_omap gpt12_ick_hw = { - .hw = { - .clk = &gpt12_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clk_ops gpt1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_GPT1_MASK, - OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, gpt1_fck_ops); - -static struct clk gpt1_ick; - -static struct clk_hw_omap gpt1_ick_hw = { - .hw = { - .clk = &gpt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt2_ick; - -static struct clk_hw_omap gpt2_ick_hw = { - .hw = { - .clk = &gpt2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT3_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt3_ick; - -static struct clk_hw_omap gpt3_ick_hw = { - .hw = { - .clk = &gpt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT4_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt4_ick; - -static struct clk_hw_omap gpt4_ick_hw = { - .hw = { - .clk = &gpt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT5_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt5_ick; - -static struct clk_hw_omap gpt5_ick_hw = { - .hw = { - .clk = &gpt5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT6_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt6_ick; - -static struct clk_hw_omap gpt6_ick_hw = { - .hw = { - .clk = &gpt6_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT7_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt7_ick; - -static struct clk_hw_omap gpt7_ick_hw = { - .hw = { - .clk = &gpt7_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT8_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt8_ick; - -static struct clk_hw_omap gpt8_ick_hw = { - .hw = { - .clk = &gpt8_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT9_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt9_ick; - -static struct clk_hw_omap gpt9_ick_hw = { - .hw = { - .clk = &gpt9_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk hdq_fck; - -static struct clk_hw_omap hdq_fck_hw = { - .hw = { - .clk = &hdq_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk hdq_ick; - -static struct clk_hw_omap hdq_ick_hw = { - .hw = { - .clk = &hdq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c1_fck; - -static struct clk_hw_omap i2c1_fck_hw = { - .hw = { - .clk = &i2c1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk i2c1_ick; - -static struct clk_hw_omap i2c1_ick_hw = { - .hw = { - .clk = &i2c1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c2_fck; - -static struct clk_hw_omap i2c2_fck_hw = { - .hw = { - .clk = &i2c2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk i2c2_ick; - -static struct clk_hw_omap i2c2_ick_hw = { - .hw = { - .clk = &i2c2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP2420_CLKSEL_IVA_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -static struct clk iva1_mpu_int_ifck; - -static const char *iva1_mpu_int_ifck_parent_names[] = { - "iva1_ifck", -}; - -static const struct clk_ops iva1_mpu_int_ifck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap_fixed_divisor_recalc, -}; - -static struct clk_hw_omap iva1_mpu_int_ifck_hw = { - .hw = { - .clk = &iva1_mpu_int_ifck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, - .clkdm_name = "iva1_clkdm", - .fixed_div = 2, -}; - -DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, - iva1_mpu_int_ifck_ops); - -static struct clk mailboxes_ick; - -static struct clk_hw_omap mailboxes_ick_hw = { - .hw = { - .clk = &mailboxes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL }, -}; - -static const char *mcbsp1_fck_parent_names[] = { - "func_96m_ck", "mcbsp_clks", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP1_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp1_ick; - -static struct clk_hw_omap mcbsp1_ick_hw = { - .hw = { - .clk = &mcbsp1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP2_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp2_ick; - -static struct clk_hw_omap mcbsp2_ick_hw = { - .hw = { - .clk = &mcbsp2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi1_fck; - -static const char *mcspi1_fck_parent_names[] = { - "func_48m_ck", -}; - -static struct clk_hw_omap mcspi1_fck_hw = { - .hw = { - .clk = &mcspi1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi1_ick; - -static struct clk_hw_omap mcspi1_ick_hw = { - .hw = { - .clk = &mcspi1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi2_fck; - -static struct clk_hw_omap mcspi2_fck_hw = { - .hw = { - .clk = &mcspi2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi2_ick; - -static struct clk_hw_omap mcspi2_ick_hw = { - .hw = { - .clk = &mcspi2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmc_fck; - -static struct clk_hw_omap mmc_fck_hw = { - .hw = { - .clk = &mmc_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmc_ick; - -static struct clk_hw_omap mmc_ick_hw = { - .hw = { - .clk = &mmc_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk mpu_wdt_fck; - -static struct clk_hw_omap mpu_wdt_fck_hw = { - .hw = { - .clk = &mpu_wdt_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk mpu_wdt_ick; - -static struct clk_hw_omap mpu_wdt_ick_hw = { - .hw = { - .clk = &mpu_wdt_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk mspro_fck; - -static struct clk_hw_omap mspro_fck_hw = { - .hw = { - .clk = &mspro_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mspro_ick; - -static struct clk_hw_omap mspro_ick_hw = { - .hw = { - .clk = &mspro_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk omapctrl_ick; - -static struct clk_hw_omap omapctrl_ick_hw = { - .hw = { - .clk = &omapctrl_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk pka_ick; - -static struct clk_hw_omap pka_ick_hw = { - .hw = { - .clk = &pka_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk rng_ick; - -static struct clk_hw_omap rng_ick_hw = { - .hw = { - .clk = &rng_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk sdma_fck; - -DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); -DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdma_ick; - -static struct clk_hw_omap sdma_ick_hw = { - .hw = { - .clk = &sdma_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdrc_ick; - -static struct clk_hw_omap sdrc_ick_hw = { - .hw = { - .clk = &sdrc_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sha_ick; - -static struct clk_hw_omap sha_ick_hw = { - .hw = { - .clk = &sha_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk ssi_l4_ick; - -static struct clk_hw_omap ssi_l4_ick_hw = { - .hw = { - .clk = &ssi_l4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *ssi_ssr_sst_fck_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", - ssi_ssr_sst_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_SSI_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, - ssi_ssr_sst_fck_parent_names, dsp_fck_ops); - -static struct clk sync_32k_ick; - -static struct clk_hw_omap sync_32k_ick_hw = { - .hw = { - .clk = &sync_32k_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL }, -}; - -static const char *sys_clkout_src_parent_names[] = { - "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, - OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm", - common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL, - OMAP2420_CLKOUT2_SOURCE_MASK, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, - OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, - OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -static struct clk uart1_fck; - -static struct clk_hw_omap uart1_fck_hw = { - .hw = { - .clk = &uart1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart1_ick; - -static struct clk_hw_omap uart1_ick_hw = { - .hw = { - .clk = &uart1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart2_fck; - -static struct clk_hw_omap uart2_fck_hw = { - .hw = { - .clk = &uart2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart2_ick; - -static struct clk_hw_omap uart2_ick_hw = { - .hw = { - .clk = &uart2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart3_fck; - -static struct clk_hw_omap uart3_fck_hw = { - .hw = { - .clk = &uart3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart3_ick; - -static struct clk_hw_omap uart3_ick_hw = { - .hw = { - .clk = &uart3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk usb_fck; - -static struct clk_hw_omap usb_fck_hw = { - .hw = { - .clk = &usb_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -static const char *usb_l4_ick_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_USB_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, - usb_l4_ick_parent_names, dsp_fck_ops); - -static struct clk virt_prcm_set; - -static const char *virt_prcm_set_parent_names[] = { - "mpu_ck", -}; - -static const struct clk_ops virt_prcm_set_ops = { - .recalc_rate = &omap2_table_mpu_recalc, - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); -DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); - -static const struct clksel_rate vlynq_fck_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel_rate vlynq_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_242X }, - { .div = 2, .val = 2, .flags = RATE_IN_242X }, - { .div = 3, .val = 3, .flags = RATE_IN_242X }, - { .div = 4, .val = 4, .flags = RATE_IN_242X }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 9, .val = 9, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 16, .val = 16, .flags = RATE_IN_242X }, - { .div = 18, .val = 18, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel vlynq_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, - { .parent = &core_ck, .rates = vlynq_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *vlynq_fck_parent_names[] = { - "func_96m_ck", "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP2420_CLKSEL_VLYNQ_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, - vlynq_fck_parent_names, dss1_fck_ops); - -static struct clk vlynq_ick; - -static struct clk_hw_omap vlynq_ick_hw = { - .hw = { - .clk = &vlynq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk wdt1_ick; - -static struct clk_hw_omap wdt1_ick_hw = { - .hw = { - .clk = &wdt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk wdt3_fck; - -static struct clk_hw_omap wdt3_fck_hw = { - .hw = { - .clk = &wdt3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk wdt3_ick; - -static struct clk_hw_omap wdt3_ick_hw = { - .hw = { - .clk = &wdt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk wdt4_fck; - -static struct clk_hw_omap wdt4_fck_hw = { - .hw = { - .clk = &wdt4_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); - -static struct clk wdt4_ick; - -static struct clk_hw_omap wdt4_ick_hw = { - .hw = { - .clk = &wdt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); - -/* - * clkdev integration - */ - -static struct omap_clk omap2420_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck), - CLK(NULL, "secure_32k_ck", &secure_32k_ck), - CLK(NULL, "osc_ck", &osc_ck), - CLK(NULL, "sys_ck", &sys_ck), - CLK(NULL, "alt_ck", &alt_ck), - CLK(NULL, "mcbsp_clks", &mcbsp_clks), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck), - CLK(NULL, "apll96_ck", &apll96_ck), - CLK(NULL, "apll54_ck", &apll54_ck), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck), - CLK(NULL, "core_ck", &core_ck), - CLK(NULL, "func_96m_ck", &func_96m_ck), - CLK(NULL, "func_48m_ck", &func_48m_ck), - CLK(NULL, "func_12m_ck", &func_12m_ck), - CLK(NULL, "sys_clkout_src", &sys_clkout_src), - CLK(NULL, "sys_clkout", &sys_clkout), - CLK(NULL, "sys_clkout2_src", &sys_clkout2_src), - CLK(NULL, "sys_clkout2", &sys_clkout2), - CLK(NULL, "emul_ck", &emul_ck), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck), - CLK(NULL, "dsp_ick", &dsp_ick), - CLK(NULL, "iva1_ifck", &iva1_ifck), - CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), - CLK(NULL, "gfx_ick", &gfx_ick), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick), - CLK(NULL, "dss_ick", &dss_ick), - CLK(NULL, "dss1_fck", &dss1_fck), - CLK(NULL, "dss2_fck", &dss2_fck), - CLK(NULL, "dss_54m_fck", &dss_54m_fck), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), - CLK(NULL, "usb_l4_ick", &usb_l4_ick), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick), - CLK(NULL, "gpt1_fck", &gpt1_fck), - CLK(NULL, "gpt2_ick", &gpt2_ick), - CLK(NULL, "gpt2_fck", &gpt2_fck), - CLK(NULL, "gpt3_ick", &gpt3_ick), - CLK(NULL, "gpt3_fck", &gpt3_fck), - CLK(NULL, "gpt4_ick", &gpt4_ick), - CLK(NULL, "gpt4_fck", &gpt4_fck), - CLK(NULL, "gpt5_ick", &gpt5_ick), - CLK(NULL, "gpt5_fck", &gpt5_fck), - CLK(NULL, "gpt6_ick", &gpt6_ick), - CLK(NULL, "gpt6_fck", &gpt6_fck), - CLK(NULL, "gpt7_ick", &gpt7_ick), - CLK(NULL, "gpt7_fck", &gpt7_fck), - CLK(NULL, "gpt8_ick", &gpt8_ick), - CLK(NULL, "gpt8_fck", &gpt8_fck), - CLK(NULL, "gpt9_ick", &gpt9_ick), - CLK(NULL, "gpt9_fck", &gpt9_fck), - CLK(NULL, "gpt10_ick", &gpt10_ick), - CLK(NULL, "gpt10_fck", &gpt10_fck), - CLK(NULL, "gpt11_ick", &gpt11_ick), - CLK(NULL, "gpt11_fck", &gpt11_fck), - CLK(NULL, "gpt12_ick", &gpt12_ick), - CLK(NULL, "gpt12_fck", &gpt12_fck), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick), - CLK(NULL, "mcspi1_ick", &mcspi1_ick), - CLK(NULL, "mcspi1_fck", &mcspi1_fck), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick), - CLK(NULL, "mcspi2_ick", &mcspi2_ick), - CLK(NULL, "mcspi2_fck", &mcspi2_fck), - CLK(NULL, "uart1_ick", &uart1_ick), - CLK(NULL, "uart1_fck", &uart1_fck), - CLK(NULL, "uart2_ick", &uart2_ick), - CLK(NULL, "uart2_fck", &uart2_fck), - CLK(NULL, "uart3_ick", &uart3_ick), - CLK(NULL, "uart3_fck", &uart3_fck), - CLK(NULL, "gpios_ick", &gpios_ick), - CLK(NULL, "gpios_fck", &gpios_fck), - CLK("omap_wdt", "ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), - CLK(NULL, "sync_32k_ick", &sync_32k_ick), - CLK(NULL, "wdt1_ick", &wdt1_ick), - CLK(NULL, "omapctrl_ick", &omapctrl_ick), - CLK("omap24xxcam", "fck", &cam_fck), - CLK(NULL, "cam_fck", &cam_fck), - CLK("omap24xxcam", "ick", &cam_ick), - CLK(NULL, "cam_ick", &cam_ick), - CLK(NULL, "mailboxes_ick", &mailboxes_ick), - CLK(NULL, "wdt4_ick", &wdt4_ick), - CLK(NULL, "wdt4_fck", &wdt4_fck), - CLK(NULL, "wdt3_ick", &wdt3_ick), - CLK(NULL, "wdt3_fck", &wdt3_fck), - CLK(NULL, "mspro_ick", &mspro_ick), - CLK(NULL, "mspro_fck", &mspro_fck), - CLK("mmci-omap.0", "ick", &mmc_ick), - CLK(NULL, "mmc_ick", &mmc_ick), - CLK("mmci-omap.0", "fck", &mmc_fck), - CLK(NULL, "mmc_fck", &mmc_fck), - CLK(NULL, "fac_ick", &fac_ick), - CLK(NULL, "fac_fck", &fac_fck), - CLK(NULL, "eac_ick", &eac_ick), - CLK(NULL, "eac_fck", &eac_fck), - CLK("omap_hdq.0", "ick", &hdq_ick), - CLK(NULL, "hdq_ick", &hdq_ick), - CLK("omap_hdq.0", "fck", &hdq_fck), - CLK(NULL, "hdq_fck", &hdq_fck), - CLK("omap_i2c.1", "ick", &i2c1_ick), - CLK(NULL, "i2c1_ick", &i2c1_ick), - CLK(NULL, "i2c1_fck", &i2c1_fck), - CLK("omap_i2c.2", "ick", &i2c2_ick), - CLK(NULL, "i2c2_ick", &i2c2_ick), - CLK(NULL, "i2c2_fck", &i2c2_fck), - CLK(NULL, "gpmc_fck", &gpmc_fck), - CLK(NULL, "sdma_fck", &sdma_fck), - CLK(NULL, "sdma_ick", &sdma_ick), - CLK(NULL, "sdrc_ick", &sdrc_ick), - CLK(NULL, "vlynq_ick", &vlynq_ick), - CLK(NULL, "vlynq_fck", &vlynq_fck), - CLK(NULL, "des_ick", &des_ick), - CLK("omap-sham", "ick", &sha_ick), - CLK(NULL, "sha_ick", &sha_ick), - CLK("omap_rng", "ick", &rng_ick), - CLK(NULL, "rng_ick", &rng_ick), - CLK("omap-aes", "ick", &aes_ick), - CLK(NULL, "aes_ick", &aes_ick), - CLK(NULL, "pka_ick", &pka_ick), - CLK(NULL, "usb_fck", &usb_fck), - CLK("musb-hdrc", "fck", &osc_ck), - CLK(NULL, "timer_32k_ck", &func_32k_ck), - CLK(NULL, "timer_sys_ck", &sys_ck), - CLK(NULL, "timer_ext_ck", &alt_ck), - CLK(NULL, "cpufreq_ck", &virt_prcm_set), -}; - - -static const char *enable_init_clks[] = { - "apll96_ck", - "apll54_ck", - "sync_32k_ick", - "omapctrl_ick", - "gpmc_fck", - "sdrc_ick", -}; - -/* - * init code - */ - -int __init omap2420_clk_init(void) -{ - prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; - cpu_mask = RATE_IN_242X; - rate_table = omap2420_rate_table; - - omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); - - omap2xxx_clkt_vps_check_bootloader_rates(); - - omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks)); - - omap2xxx_clkt_vps_late_init(); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); - - return 0; -} diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c deleted file mode 100644 index 5e4b037bb24c..000000000000 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ /dev/null @@ -1,2048 +0,0 @@ -/* - * OMAP2430 clock data - * - * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/clk-private.h> -#include <linux/list.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx.h" -#include "prm2xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR - -/* - * 2430 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); - -DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); - -static struct clk osc_ck; - -static const struct clk_ops osc_ck_ops = { - .enable = &omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, - .recalc_rate = &omap2_osc_clk_recalc, -}; - -static struct clk_hw_omap osc_ck_hw = { - .hw = { - .clk = &osc_ck, - }, -}; - -static struct clk osc_ck = { - .name = "osc_ck", - .ops = &osc_ck_ops, - .hw = &osc_ck_hw.hw, - .flags = CLK_IS_ROOT, -}; - -DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -static struct clk sys_ck; - -static const char *sys_ck_parent_names[] = { - "osc_ck", -}; - -static const struct clk_ops sys_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2xxx_sys_clk_recalc, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -static struct clk dpll_ck; - -static const char *dpll_ck_parent_names[] = { - "sys_ck", -}; - -static const struct clk_ops dpll_ck_ops = { - .init = &omap2_init_clk_clkdm, - .get_parent = &omap2_init_dpll_parent, - .recalc_rate = &omap2_dpllcore_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk_hw_omap dpll_ck_hw = { - .hw = { - .clk = &dpll_ck, - }, - .ops = &clkhwops_omap2xxx_dpll, - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); - -static struct clk core_ck; - -static const char *core_ck_parent_names[] = { - "dpll_ck", -}; - -static const struct clk_ops core_ck_ops = { - .init = &omap2_init_clk_clkdm, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); -DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); - -DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk aes_ick; - -static const char *aes_ick_parent_names[] = { - "l4_ck", -}; - -static const struct clk_ops aes_ick_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap aes_ick_hw = { - .hw = { - .clk = &aes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk apll54_ck; - -static const struct clk_ops apll54_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll54_enable, - .disable = &omap2_clk_apll54_disable, - .recalc_rate = &omap2_clk_apll54_recalc, -}; - -static struct clk_hw_omap apll54_ck_hw = { - .hw = { - .clk = &apll54_ck, - }, - .ops = &clkhwops_apll54, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); - -static struct clk apll96_ck; - -static const struct clk_ops apll96_ck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clk_apll96_enable, - .disable = &omap2_clk_apll96_disable, - .recalc_rate = &omap2_clk_apll96_recalc, -}; - -static struct clk_hw_omap apll96_ck_hw = { - .hw = { - .clk = &apll96_ck, - }, - .ops = &clkhwops_apll96, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); - -static const char *func_96m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, - OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); - -static struct clk cam_fck; - -static const char *cam_fck_parent_names[] = { - "func_96m_ck", -}; - -static struct clk_hw_omap cam_fck_hw = { - .hw = { - .clk = &cam_fck, - }, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk cam_ick; - -static struct clk_hw_omap cam_ick_hw = { - .hw = { - .clk = &cam_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk des_ick; - -static struct clk_hw_omap des_ick_hw = { - .hw = { - .clk = &des_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dsp_fck_parent_names[] = { - "core_ck", -}; - -static struct clk dsp_fck; - -static const struct clk_ops dsp_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - dsp_fck_parent_names, dsp_fck_ops); - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *dss1_fck_parent_names[] = { - "sys_ck", "core_ck", -}; - -static const struct clk_ops dss1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS1_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS1_SHIFT, NULL, - dss1_fck_parent_names, dss1_fck_ops); - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL }, -}; - -static const char *func_48m_ck_parent_names[] = { - "apll96_ck", "alt_ck", -}; - -static struct clk func_48m_ck; - -static const struct clk_ops func_48m_ck_ops = { - .init = &omap2_init_clk_clkdm, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static struct clk_hw_omap func_48m_ck_hw = { - .hw = { - .clk = &func_48m_ck, - }, - .clksel = func_48m_clksel, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL }, -}; - -static const char *dss2_fck_parent_names[] = { - "sys_ck", "func_48m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_DSS2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_DSS2_SHIFT, NULL, - dss2_fck_parent_names, dss1_fck_ops); - -static const char *func_54m_ck_parent_names[] = { - "apll54_ck", "alt_ck", -}; - -DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, - OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); - -static struct clk dss_54m_fck; - -static const char *dss_54m_fck_parent_names[] = { - "func_54m_ck", -}; - -static struct clk_hw_omap dss_54m_fck_hw = { - .hw = { - .clk = &dss_54m_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); - -static struct clk dss_ick; - -static struct clk_hw_omap dss_ick_hw = { - .hw = { - .clk = &dss_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", -}; - -DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk emul_ck; - -static struct clk_hw_omap emul_ck_hw = { - .hw = { - .clk = &emul_ck, - }, - .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); - -static struct clk fac_fck; - -static const char *fac_fck_parent_names[] = { - "func_12m_ck", -}; - -static struct clk_hw_omap fac_fck_hw = { - .hw = { - .clk = &fac_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk fac_ick; - -static struct clk_hw_omap fac_ick_hw = { - .hw = { - .clk = &fac_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static const char *gfx_2d_fck_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, - OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - OMAP_CLKSEL_GFX_MASK, - OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, - gfx_2d_fck_parent_names, dsp_fck_ops); - -static struct clk gfx_ick; - -static const char *gfx_ick_parent_names[] = { - "core_l3_ck", -}; - -static struct clk_hw_omap gfx_ick_hw = { - .hw = { - .clk = &gfx_ick, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .clkdm_name = "gfx_clkdm", -}; - -DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk gpio5_fck; - -static const char *gpio5_fck_parent_names[] = { - "func_32k_ck", -}; - -static struct clk_hw_omap gpio5_fck_hw = { - .hw = { - .clk = &gpio5_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk gpio5_ick; - -static struct clk_hw_omap gpio5_ick_hw = { - .hw = { - .clk = &gpio5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk gpios_fck; - -static struct clk_hw_omap gpios_fck_hw = { - .hw = { - .clk = &gpios_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk gpios_ick; - -static const char *gpios_ick_parent_names[] = { - "sys_ck", -}; - -static struct clk_hw_omap gpios_ick_hw = { - .hw = { - .clk = &gpios_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk gpmc_fck; - -static struct clk_hw_omap gpmc_fck_hw = { - .hw = { - .clk = &gpmc_fck, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); - -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static const char *gpt10_fck_parent_names[] = { - "func_32k_ck", "sys_ck", "alt_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT10_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt10_ick; - -static struct clk_hw_omap gpt10_ick_hw = { - .hw = { - .clk = &gpt10_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT11_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt11_ick; - -static struct clk_hw_omap gpt11_ick_hw = { - .hw = { - .clk = &gpt11_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT12_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt12_ick; - -static struct clk_hw_omap gpt12_ick_hw = { - .hw = { - .clk = &gpt12_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clk_ops gpt1_fck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_GPT1_MASK, - OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, gpt1_fck_ops); - -static struct clk gpt1_ick; - -static struct clk_hw_omap gpt1_ick_hw = { - .hw = { - .clk = &gpt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT2_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt2_ick; - -static struct clk_hw_omap gpt2_ick_hw = { - .hw = { - .clk = &gpt2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT3_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt3_ick; - -static struct clk_hw_omap gpt3_ick_hw = { - .hw = { - .clk = &gpt3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT4_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt4_ick; - -static struct clk_hw_omap gpt4_ick_hw = { - .hw = { - .clk = &gpt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT5_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt5_ick; - -static struct clk_hw_omap gpt5_ick_hw = { - .hw = { - .clk = &gpt5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT6_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt6_ick; - -static struct clk_hw_omap gpt6_ick_hw = { - .hw = { - .clk = &gpt6_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT7_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt7_ick; - -static struct clk_hw_omap gpt7_ick_hw = { - .hw = { - .clk = &gpt7_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk gpt8_fck; - -DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT8_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt8_ick; - -static struct clk_hw_omap gpt8_ick_hw = { - .hw = { - .clk = &gpt8_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - OMAP24XX_CLKSEL_GPT9_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, - gpt10_fck_parent_names, dss1_fck_ops); - -static struct clk gpt9_ick; - -static struct clk_hw_omap gpt9_ick_hw = { - .hw = { - .clk = &gpt9_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk hdq_fck; - -static struct clk_hw_omap hdq_fck_hw = { - .hw = { - .clk = &hdq_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); - -static struct clk hdq_ick; - -static struct clk_hw_omap hdq_ick_hw = { - .hw = { - .clk = &hdq_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c1_ick; - -static struct clk_hw_omap i2c1_ick_hw = { - .hw = { - .clk = &i2c1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2c2_ick; - -static struct clk_hw_omap i2c2_ick_hw = { - .hw = { - .clk = &i2c2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk i2chs1_fck; - -static struct clk_hw_omap i2chs1_fck_hw = { - .hw = { - .clk = &i2chs1_fck, - }, - .ops = &clkhwops_omap2430_i2chs_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk i2chs2_fck; - -static struct clk_hw_omap i2chs2_fck_hw = { - .hw = { - .clk = &i2chs2_fck, - }, - .ops = &clkhwops_omap2430_i2chs_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk icr_ick; - -static struct clk_hw_omap icr_ick_hw = { - .hw = { - .clk = &icr_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP2430_EN_ICR_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL }, -}; - -static const char *iva2_1_ick_parent_names[] = { - "dsp_fck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_DSP_IF_MASK, - OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, - iva2_1_ick_parent_names, dsp_fck_ops); - -static struct clk mailboxes_ick; - -static struct clk_hw_omap mailboxes_ick_hw = { - .hw = { - .clk = &mailboxes_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL }, -}; - -static const char *mcbsp1_fck_parent_names[] = { - "func_96m_ck", "mcbsp_clks", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP1_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp1_ick; - -static struct clk_hw_omap mcbsp1_ick_hw = { - .hw = { - .clk = &mcbsp1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - OMAP2_MCBSP2_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp2_ick; - -static struct clk_hw_omap mcbsp2_ick_hw = { - .hw = { - .clk = &mcbsp2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP3_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp3_ick; - -static struct clk_hw_omap mcbsp3_ick_hw = { - .hw = { - .clk = &mcbsp3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP4_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp4_ick; - -static struct clk_hw_omap mcbsp4_ick_hw = { - .hw = { - .clk = &mcbsp4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); - -DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, - OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - OMAP2_MCBSP5_CLKS_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, - mcbsp1_fck_parent_names, dss1_fck_ops); - -static struct clk mcbsp5_ick; - -static struct clk_hw_omap mcbsp5_ick_hw = { - .hw = { - .clk = &mcbsp5_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi1_fck; - -static const char *mcspi1_fck_parent_names[] = { - "func_48m_ck", -}; - -static struct clk_hw_omap mcspi1_fck_hw = { - .hw = { - .clk = &mcspi1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi1_ick; - -static struct clk_hw_omap mcspi1_ick_hw = { - .hw = { - .clk = &mcspi1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi2_fck; - -static struct clk_hw_omap mcspi2_fck_hw = { - .hw = { - .clk = &mcspi2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi2_ick; - -static struct clk_hw_omap mcspi2_ick_hw = { - .hw = { - .clk = &mcspi2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mcspi3_fck; - -static struct clk_hw_omap mcspi3_fck_hw = { - .hw = { - .clk = &mcspi3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk mcspi3_ick; - -static struct clk_hw_omap mcspi3_ick_hw = { - .hw = { - .clk = &mcspi3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate mdm_ick_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_243X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X }, - { .div = 6, .val = 6, .flags = RATE_IN_243X }, - { .div = 9, .val = 9, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel mdm_ick_clksel[] = { - { .parent = &core_ck, .rates = mdm_ick_core_rates }, - { .parent = NULL }, -}; - -static const char *mdm_ick_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, - OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), - OMAP2430_CLKSEL_MDM_MASK, - OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), - OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, - &clkhwops_iclk_wait, mdm_ick_parent_names, - dsp_fck_ops); - -static struct clk mdm_intc_ick; - -static struct clk_hw_omap mdm_intc_ick_hw = { - .hw = { - .clk = &mdm_intc_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mdm_osc_ck; - -static struct clk_hw_omap mdm_osc_ck_hw = { - .hw = { - .clk = &mdm_osc_ck, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), - .enable_bit = OMAP2430_EN_OSC_SHIFT, - .clkdm_name = "mdm_clkdm", -}; - -DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); - -static struct clk mmchs1_fck; - -static struct clk_hw_omap mmchs1_fck_hw = { - .hw = { - .clk = &mmchs1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmchs1_ick; - -static struct clk_hw_omap mmchs1_ick_hw = { - .hw = { - .clk = &mmchs1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmchs2_fck; - -static struct clk_hw_omap mmchs2_fck_hw = { - .hw = { - .clk = &mmchs2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mmchs2_ick; - -static struct clk_hw_omap mmchs2_ick_hw = { - .hw = { - .clk = &mmchs2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk mmchsdb1_fck; - -static struct clk_hw_omap mmchsdb1_fck_hw = { - .hw = { - .clk = &mmchsdb1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk mmchsdb2_fck; - -static struct clk_hw_omap mmchsdb2_fck_hw = { - .hw = { - .clk = &mmchsdb2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); - -DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, - OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -static struct clk mpu_wdt_fck; - -static struct clk_hw_omap mpu_wdt_fck_hw = { - .hw = { - .clk = &mpu_wdt_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk mpu_wdt_ick; - -static struct clk_hw_omap mpu_wdt_ick_hw = { - .hw = { - .clk = &mpu_wdt_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk mspro_fck; - -static struct clk_hw_omap mspro_fck_hw = { - .hw = { - .clk = &mspro_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); - -static struct clk mspro_ick; - -static struct clk_hw_omap mspro_ick_hw = { - .hw = { - .clk = &mspro_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk omapctrl_ick; - -static struct clk_hw_omap omapctrl_ick_hw = { - .hw = { - .clk = &omapctrl_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk pka_ick; - -static struct clk_hw_omap pka_ick_hw = { - .hw = { - .clk = &pka_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk rng_ick; - -static struct clk_hw_omap rng_ick_hw = { - .hw = { - .clk = &rng_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk sdma_fck; - -DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); -DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdma_ick; - -static struct clk_hw_omap sdma_ick_hw = { - .hw = { - .clk = &sdma_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sdrc_ick; - -static struct clk_hw_omap sdrc_ick_hw = { - .hw = { - .clk = &sdrc_ick, - }, - .ops = &clkhwops_iclk, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP2430_EN_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); - -static struct clk sha_ick; - -static struct clk_hw_omap sha_ick_hw = { - .hw = { - .clk = &sha_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk ssi_l4_ick; - -static struct clk_hw_omap ssi_l4_ick_hw = { - .hw = { - .clk = &ssi_l4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL }, -}; - -static const char *ssi_ssr_sst_fck_parent_names[] = { - "core_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", - ssi_ssr_sst_fck_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_SSI_MASK, - OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, - ssi_ssr_sst_fck_parent_names, dsp_fck_ops); - -static struct clk sync_32k_ick; - -static struct clk_hw_omap sync_32k_ick_hw = { - .hw = { - .clk = &sync_32k_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); - -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL }, -}; - -static const char *sys_clkout_src_parent_names[] = { - "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, - NULL, sys_clkout_src_parent_names, gpt1_fck_ops); - -DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, - OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, - OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -static struct clk uart1_fck; - -static struct clk_hw_omap uart1_fck_hw = { - .hw = { - .clk = &uart1_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart1_ick; - -static struct clk_hw_omap uart1_ick_hw = { - .hw = { - .clk = &uart1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart2_fck; - -static struct clk_hw_omap uart2_fck_hw = { - .hw = { - .clk = &uart2_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart2_ick; - -static struct clk_hw_omap uart2_ick_hw = { - .hw = { - .clk = &uart2_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk uart3_fck; - -static struct clk_hw_omap uart3_fck_hw = { - .hw = { - .clk = &uart3_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static struct clk uart3_ick; - -static struct clk_hw_omap uart3_ick_hw = { - .hw = { - .clk = &uart3_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); - -static struct clk usb_fck; - -static struct clk_hw_omap usb_fck_hw = { - .hw = { - .clk = &usb_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); - -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -static const char *usb_l4_ick_parent_names[] = { - "core_l3_ck", -}; - -DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, - OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - OMAP24XX_CLKSEL_USB_MASK, - OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, - usb_l4_ick_parent_names, dsp_fck_ops); - -static struct clk usbhs_ick; - -static struct clk_hw_omap usbhs_ick_hw = { - .hw = { - .clk = &usbhs_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_USBHS_SHIFT, - .clkdm_name = "core_l3_clkdm", -}; - -DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); - -static struct clk virt_prcm_set; - -static const char *virt_prcm_set_parent_names[] = { - "mpu_ck", -}; - -static const struct clk_ops virt_prcm_set_ops = { - .recalc_rate = &omap2_table_mpu_recalc, - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - -DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); -DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); - -static struct clk wdt1_ick; - -static struct clk_hw_omap wdt1_ick_hw = { - .hw = { - .clk = &wdt1_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); - -static struct clk wdt4_fck; - -static struct clk_hw_omap wdt4_fck_hw = { - .hw = { - .clk = &wdt4_fck, - }, - .ops = &clkhwops_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); - -static struct clk wdt4_ick; - -static struct clk_hw_omap wdt4_ick_hw = { - .hw = { - .clk = &wdt4_ick, - }, - .ops = &clkhwops_iclk_wait, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .clkdm_name = "core_l4_clkdm", -}; - -DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); - -/* - * clkdev integration - */ - -static struct omap_clk omap2430_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck), - CLK(NULL, "secure_32k_ck", &secure_32k_ck), - CLK(NULL, "osc_ck", &osc_ck), - CLK("twl", "fck", &osc_ck), - CLK(NULL, "sys_ck", &sys_ck), - CLK(NULL, "alt_ck", &alt_ck), - CLK(NULL, "mcbsp_clks", &mcbsp_clks), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck), - CLK(NULL, "apll96_ck", &apll96_ck), - CLK(NULL, "apll54_ck", &apll54_ck), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck), - CLK(NULL, "core_ck", &core_ck), - CLK(NULL, "func_96m_ck", &func_96m_ck), - CLK(NULL, "func_48m_ck", &func_48m_ck), - CLK(NULL, "func_12m_ck", &func_12m_ck), - CLK(NULL, "sys_clkout_src", &sys_clkout_src), - CLK(NULL, "sys_clkout", &sys_clkout), - CLK(NULL, "emul_ck", &emul_ck), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck), - CLK(NULL, "iva2_1_ick", &iva2_1_ick), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), - CLK(NULL, "gfx_ick", &gfx_ick), - /* Modem domain clocks */ - CLK(NULL, "mdm_ick", &mdm_ick), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick), - CLK(NULL, "dss_ick", &dss_ick), - CLK(NULL, "dss1_fck", &dss1_fck), - CLK(NULL, "dss2_fck", &dss2_fck), - CLK(NULL, "dss_54m_fck", &dss_54m_fck), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), - CLK(NULL, "usb_l4_ick", &usb_l4_ick), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick), - CLK(NULL, "gpt1_fck", &gpt1_fck), - CLK(NULL, "gpt2_ick", &gpt2_ick), - CLK(NULL, "gpt2_fck", &gpt2_fck), - CLK(NULL, "gpt3_ick", &gpt3_ick), - CLK(NULL, "gpt3_fck", &gpt3_fck), - CLK(NULL, "gpt4_ick", &gpt4_ick), - CLK(NULL, "gpt4_fck", &gpt4_fck), - CLK(NULL, "gpt5_ick", &gpt5_ick), - CLK(NULL, "gpt5_fck", &gpt5_fck), - CLK(NULL, "gpt6_ick", &gpt6_ick), - CLK(NULL, "gpt6_fck", &gpt6_fck), - CLK(NULL, "gpt7_ick", &gpt7_ick), - CLK(NULL, "gpt7_fck", &gpt7_fck), - CLK(NULL, "gpt8_ick", &gpt8_ick), - CLK(NULL, "gpt8_fck", &gpt8_fck), - CLK(NULL, "gpt9_ick", &gpt9_ick), - CLK(NULL, "gpt9_fck", &gpt9_fck), - CLK(NULL, "gpt10_ick", &gpt10_ick), - CLK(NULL, "gpt10_fck", &gpt10_fck), - CLK(NULL, "gpt11_ick", &gpt11_ick), - CLK(NULL, "gpt11_fck", &gpt11_fck), - CLK(NULL, "gpt12_ick", &gpt12_ick), - CLK(NULL, "gpt12_fck", &gpt12_fck), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), - CLK(NULL, "mcbsp4_ick", &mcbsp4_ick), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick), - CLK(NULL, "mcspi1_ick", &mcspi1_ick), - CLK(NULL, "mcspi1_fck", &mcspi1_fck), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick), - CLK(NULL, "mcspi2_ick", &mcspi2_ick), - CLK(NULL, "mcspi2_fck", &mcspi2_fck), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick), - CLK(NULL, "mcspi3_ick", &mcspi3_ick), - CLK(NULL, "mcspi3_fck", &mcspi3_fck), - CLK(NULL, "uart1_ick", &uart1_ick), - CLK(NULL, "uart1_fck", &uart1_fck), - CLK(NULL, "uart2_ick", &uart2_ick), - CLK(NULL, "uart2_fck", &uart2_fck), - CLK(NULL, "uart3_ick", &uart3_ick), - CLK(NULL, "uart3_fck", &uart3_fck), - CLK(NULL, "gpios_ick", &gpios_ick), - CLK(NULL, "gpios_fck", &gpios_fck), - CLK("omap_wdt", "ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), - CLK(NULL, "sync_32k_ick", &sync_32k_ick), - CLK(NULL, "wdt1_ick", &wdt1_ick), - CLK(NULL, "omapctrl_ick", &omapctrl_ick), - CLK(NULL, "icr_ick", &icr_ick), - CLK("omap24xxcam", "fck", &cam_fck), - CLK(NULL, "cam_fck", &cam_fck), - CLK("omap24xxcam", "ick", &cam_ick), - CLK(NULL, "cam_ick", &cam_ick), - CLK(NULL, "mailboxes_ick", &mailboxes_ick), - CLK(NULL, "wdt4_ick", &wdt4_ick), - CLK(NULL, "wdt4_fck", &wdt4_fck), - CLK(NULL, "mspro_ick", &mspro_ick), - CLK(NULL, "mspro_fck", &mspro_fck), - CLK(NULL, "fac_ick", &fac_ick), - CLK(NULL, "fac_fck", &fac_fck), - CLK("omap_hdq.0", "ick", &hdq_ick), - CLK(NULL, "hdq_ick", &hdq_ick), - CLK("omap_hdq.1", "fck", &hdq_fck), - CLK(NULL, "hdq_fck", &hdq_fck), - CLK("omap_i2c.1", "ick", &i2c1_ick), - CLK(NULL, "i2c1_ick", &i2c1_ick), - CLK(NULL, "i2chs1_fck", &i2chs1_fck), - CLK("omap_i2c.2", "ick", &i2c2_ick), - CLK(NULL, "i2c2_ick", &i2c2_ick), - CLK(NULL, "i2chs2_fck", &i2chs2_fck), - CLK(NULL, "gpmc_fck", &gpmc_fck), - CLK(NULL, "sdma_fck", &sdma_fck), - CLK(NULL, "sdma_ick", &sdma_ick), - CLK(NULL, "sdrc_ick", &sdrc_ick), - CLK(NULL, "des_ick", &des_ick), - CLK("omap-sham", "ick", &sha_ick), - CLK(NULL, "sha_ick", &sha_ick), - CLK("omap_rng", "ick", &rng_ick), - CLK(NULL, "rng_ick", &rng_ick), - CLK("omap-aes", "ick", &aes_ick), - CLK(NULL, "aes_ick", &aes_ick), - CLK(NULL, "pka_ick", &pka_ick), - CLK(NULL, "usb_fck", &usb_fck), - CLK("musb-omap2430", "ick", &usbhs_ick), - CLK(NULL, "usbhs_ick", &usbhs_ick), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick), - CLK(NULL, "mmchs1_ick", &mmchs1_ick), - CLK(NULL, "mmchs1_fck", &mmchs1_fck), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick), - CLK(NULL, "mmchs2_ick", &mmchs2_ick), - CLK(NULL, "mmchs2_fck", &mmchs2_fck), - CLK(NULL, "gpio5_ick", &gpio5_ick), - CLK(NULL, "gpio5_fck", &gpio5_fck), - CLK(NULL, "mdm_intc_ick", &mdm_intc_ick), - CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck), - CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck), - CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck), - CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck), - CLK(NULL, "timer_32k_ck", &func_32k_ck), - CLK(NULL, "timer_sys_ck", &sys_ck), - CLK(NULL, "timer_ext_ck", &alt_ck), - CLK(NULL, "cpufreq_ck", &virt_prcm_set), -}; - -static const char *enable_init_clks[] = { - "apll96_ck", - "apll54_ck", - "sync_32k_ick", - "omapctrl_ick", - "gpmc_fck", - "sdrc_ick", -}; - -/* - * init code - */ - -int __init omap2430_clk_init(void) -{ - prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; - cpu_mask = RATE_IN_243X; - rate_table = omap2430_rate_table; - - omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); - - omap2xxx_clkt_vps_check_bootloader_rates(); - - omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks)); - - omap2xxx_clkt_vps_late_init(); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (clk_get_rate(&sys_ck) / 1000000), - (clk_get_rate(&sys_ck) / 100000) % 10, - (clk_get_rate(&dpll_ck) / 1000000), - (clk_get_rate(&mpu_ck) / 1000000)); - - return 0; -} diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c deleted file mode 100644 index 0717dff1bc04..000000000000 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * OMAP2xxx osc_clk-specific clock code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include "clock.h" -#include "clock2xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" - -/* - * XXX This does not actually enable the osc_ck, since the osc_ck must - * be running for this function to be called. Instead, this function - * is used to disable an autoidle mode on the osc_ck. The existing - * clk_enable/clk_disable()-based usecounting for osc_ck should be - * replaced with autoidle-based usecounting. - */ -int omap2_enable_osc_ck(struct clk_hw *clk) -{ - u32 pcc; - - pcc = readl_relaxed(prcm_clksrc_ctrl); - - writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); - - return 0; -} - -/* - * XXX This does not actually disable the osc_ck, since doing so would - * immediately halt the system. Instead, this function is used to - * enable an autoidle mode on the osc_ck. The existing - * clk_enable/clk_disable()-based usecounting for osc_ck should be - * replaced with autoidle-based usecounting. - */ -void omap2_disable_osc_ck(struct clk_hw *clk) -{ - u32 pcc; - - pcc = readl_relaxed(prcm_clksrc_ctrl); - - writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); -} - -unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, - unsigned long parent_rate) -{ - return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); -} diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c deleted file mode 100644 index 58dd3a9b726c..000000000000 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * OMAP2xxx sys_clk-specific clock code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include "clock.h" -#include "clock2xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" - -void __iomem *prcm_clksrc_ctrl; - -u32 omap2xxx_get_sysclkdiv(void) -{ - u32 div; - - div = readl_relaxed(prcm_clksrc_ctrl); - div &= OMAP_SYSCLKDIV_MASK; - div >>= OMAP_SYSCLKDIV_SHIFT; - - return div; -} - -unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, - unsigned long parent_rate) -{ - return parent_rate / omap2xxx_get_sysclkdiv(); -} diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 67fd26a18441..f251a14cbf16 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -21,10 +21,7 @@ #include <asm/div64.h> -#include "soc.h" #include "clock.h" -#include "cm-regbits-24xx.h" -#include "cm-regbits-34xx.h" /* DPLL rate rounding: minimum DPLL multiplier, divider values */ #define DPLL_MIN_MULTIPLIER 2 @@ -44,20 +41,12 @@ #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) -/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ -#define OMAP3430_DPLL_FINT_BAND1_MIN 750000 -#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 -#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 -#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 - /* * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. * From device data manual section 4.3 "DPLL and DLL Specifications". */ #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 -#define OMAP3PLUS_DPLL_FINT_MIN 32000 -#define OMAP3PLUS_DPLL_FINT_MAX 52000000 /* _dpll_test_fint() return codes */ #define DPLL_FINT_UNDERFLOW -1 @@ -87,33 +76,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) /* DPLL divider must result in a valid jitter correction val */ fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; - if (cpu_is_omap24xx()) { - /* Should not be called for OMAP2, so warn if it is called */ - WARN(1, "No fint limits available for OMAP2!\n"); - return DPLL_FINT_INVALID; - } else if (cpu_is_omap3430()) { - fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; - fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; - } else if (dd->flags & DPLL_J_TYPE) { + if (dd->flags & DPLL_J_TYPE) { fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; } else { - fint_min = OMAP3PLUS_DPLL_FINT_MIN; - fint_max = OMAP3PLUS_DPLL_FINT_MAX; + fint_min = ti_clk_features.fint_min; + fint_max = ti_clk_features.fint_max; + } + + if (!fint_min || !fint_max) { + WARN(1, "No fint limits available!\n"); + return DPLL_FINT_INVALID; } - if (fint < fint_min) { + if (fint < ti_clk_features.fint_min) { pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", n); dd->max_divider = n; ret = DPLL_FINT_UNDERFLOW; - } else if (fint > fint_max) { + } else if (fint > ti_clk_features.fint_max) { pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", n); dd->min_divider = n; ret = DPLL_FINT_INVALID; - } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && - fint < OMAP3430_DPLL_FINT_BAND2_MIN) { + } else if (fint > ti_clk_features.fint_band1_max && + fint < ti_clk_features.fint_band2_min) { pr_debug("rejecting n=%d due to Fint failure\n", n); ret = DPLL_FINT_INVALID; } @@ -185,6 +172,34 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, return r; } +/** + * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not + * @v: bitfield value of the DPLL enable + * + * Checks given DPLL enable bitfield to see whether the DPLL is in bypass + * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise. + */ +static int _omap2_dpll_is_in_bypass(u32 v) +{ + u8 mask, val; + + mask = ti_clk_features.dpll_bypass_vals; + + /* + * Each set bit in the mask corresponds to a bypass value equal + * to the bitshift. Go through each set-bit in the mask and + * compare against the given register value. + */ + while (mask) { + val = __ffs(mask); + mask ^= (1 << val); + if (v == val) + return 1; + } + + return 0; +} + /* Public functions */ u8 omap2_init_dpll_parent(struct clk_hw *hw) { @@ -201,20 +216,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) v >>= __ffs(dd->enable_mask); /* Reparent the struct clk in case the dpll is in bypass */ - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - return 1; - } + if (_omap2_dpll_is_in_bypass(v)) + return 1; + return 0; } @@ -247,20 +251,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return __clk_get_rate(dd->clk_bypass); - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return __clk_get_rate(dd->clk_bypass); - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - return __clk_get_rate(dd->clk_bypass); - } + if (_omap2_dpll_is_in_bypass(v)) + return __clk_get_rate(dd->clk_bypass); v = omap2_clk_readl(clk, dd->mult_div1_reg); dpll_mult = v & dd->mult_mask; @@ -293,10 +285,13 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, { struct clk_hw_omap *clk = to_clk_hw_omap(hw); int m, n, r, scaled_max_m; + int min_delta_m = INT_MAX, min_delta_n = INT_MAX; unsigned long scaled_rt_rp; unsigned long new_rate = 0; struct dpll_data *dd; unsigned long ref_rate; + long delta; + long prev_min_delta = LONG_MAX; const char *clk_name; if (!clk || !clk->dpll_data) @@ -342,23 +337,34 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, if (r == DPLL_MULT_UNDERFLOW) continue; + /* skip rates above our target rate */ + delta = target_rate - new_rate; + if (delta < 0) + continue; + + if (delta < prev_min_delta) { + prev_min_delta = delta; + min_delta_m = m; + min_delta_n = n; + } + pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n", clk_name, m, n, new_rate); - if (target_rate == new_rate) { - dd->last_rounded_m = m; - dd->last_rounded_n = n; - dd->last_rounded_rate = target_rate; + if (delta == 0) break; - } } - if (target_rate != new_rate) { + if (prev_min_delta == LONG_MAX) { pr_debug("clock: %s: cannot round to rate %lu\n", clk_name, target_rate); return ~0; } - return target_rate; + dd->last_rounded_m = min_delta_m; + dd->last_rounded_n = min_delta_n; + dd->last_rounded_rate = target_rate - prev_min_delta; + + return dd->last_rounded_rate; } diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index 333f0a666171..55eb579aeae1 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -14,11 +14,11 @@ #include <linux/clk-provider.h> #include <linux/io.h> - #include "clock.h" -#include "clock2xxx.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-24xx.h" + +/* Register offsets */ +#define CM_AUTOIDLE 0x30 +#define CM_ICLKEN 0x10 /* Private functions */ diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 591581a66532..500530d1364a 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -47,6 +47,24 @@ u16 cpu_mask; /* + * Clock features setup. Used instead of CPU type checks. + */ +struct ti_clk_features ti_clk_features; + +/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ +#define OMAP3430_DPLL_FINT_BAND1_MIN 750000 +#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 +#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 +#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 + +/* + * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. + * From device data manual section 4.3 "DPLL and DLL Specifications". + */ +#define OMAP3PLUS_DPLL_FINT_MIN 32000 +#define OMAP3PLUS_DPLL_FINT_MAX 52000000 + +/* * clkdm_control: if true, then when a clock is enabled in the * hardware, its clockdomain will first be enabled; and when a clock * is disabled in the hardware, its clockdomain will be disabled @@ -82,27 +100,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) } /* - * Used for clocks that have the same value as the parent clock, - * divided by some factor - */ -unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_hw_omap *oclk; - - if (!hw) { - pr_warn("%s: hw is NULL\n", __func__); - return -EINVAL; - } - - oclk = to_clk_hw_omap(hw); - - WARN_ON(!oclk->fixed_div); - - return parent_rate / oclk->fixed_div; -} - -/* * OMAP2+ specific clock functions */ @@ -287,13 +284,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, * 34xx reverses this, just to keep us on our toes * AM35xx uses both, depending on the module. */ - if (cpu_is_omap24xx()) - *idlest_val = OMAP24XX_CM_IDLEST_VAL; - else if (cpu_is_omap34xx()) - *idlest_val = OMAP34XX_CM_IDLEST_VAL; - else - BUG(); - + *idlest_val = ti_clk_features.cm_idlest_val; } /** @@ -731,3 +722,53 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(core_ck) / 1000000), (clk_get_rate(mpu_ck) / 1000000)); } + +/** + * ti_clk_init_features - init clock features struct for the SoC + * + * Initializes the clock features struct based on the SoC type. + */ +void __init ti_clk_init_features(void) +{ + /* Fint setup for DPLLs */ + if (cpu_is_omap3430()) { + ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; + ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; + ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; + ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; + } else { + ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; + ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; + } + + /* Bypass value setup for DPLLs */ + if (cpu_is_omap24xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP2XXX_EN_DPLL_FRBYPASS); + } else if (cpu_is_omap34xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP3XXX_EN_DPLL_FRBYPASS); + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || + soc_is_omap54xx() || soc_is_dra7xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | + (1 << OMAP4XXX_EN_DPLL_MNBYPASS); + } + + /* Jitter correction only available on OMAP343X */ + if (cpu_is_omap343x()) + ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; + + /* Idlest value for interface clocks. + * 24xx uses 0 to indicate not ready, and 1 to indicate ready. + * 34xx reverses this, just to keep us on our toes + * AM35xx uses both, depending on the module. + */ + if (cpu_is_omap24xx()) + ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; + else if (cpu_is_omap34xx()) + ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; +} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 12f54d428d7c..4592a2762592 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -101,31 +101,6 @@ struct clockdomain; }; \ DEFINE_STRUCT_CLK(_name, _parent_names, _ops); -#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ - _parent_ptr, _flags, \ - _clksel_reg, _clksel_mask) \ - static const struct clksel _name##_div[] = { \ - { \ - .parent = _parent_ptr, \ - .rates = div31_1to31_rates \ - }, \ - { .parent = NULL }, \ - }; \ - static struct clk _name; \ - static const char *_name##_parent_names[] = { \ - _parent_name, \ - }; \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .clksel = _name##_div, \ - .clksel_reg = _clksel_reg, \ - .clksel_mask = _clksel_mask, \ - .ops = &clkhwops_omap4_dpllmx, \ - }; \ - DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); - /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) @@ -178,9 +153,6 @@ struct clksel { const struct clksel_rate *rates; }; -unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, - unsigned long parent_rate); - /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 @@ -248,6 +220,23 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); extern u16 cpu_mask; +/* + * Clock features setup. Used instead of CPU type checks. + */ +struct ti_clk_features { + u32 flags; + long fint_min; + long fint_max; + long fint_band1_max; + long fint_band2_min; + u8 dpll_bypass_vals; + u8 cm_idlest_val; +}; + +#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) + +extern struct ti_clk_features ti_clk_features; + extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_dummy; extern const struct clkops clkops_omap2_dflt; @@ -286,4 +275,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); extern void omap_clocks_register(struct omap_clk *oclks, int cnt); + +void __init ti_clk_init_features(void); #endif diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 45f41a411603..a090225ceeba 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -45,8 +45,6 @@ int omap2430_clk_init(void); #define omap2430_clk_init() do { } while(0) #endif -extern void __iomem *prcm_clksrc_ctrl; - extern struct clk_hw *dclk_hw; int omap2_enable_osc_ck(struct clk_hw *hw); void omap2_disable_osc_ck(struct clk_hw *hw); diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 8538669cc2ad..d7a5d11cbcbf 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -107,6 +107,7 @@ #define OMAP24XX_AUTO_DPLL_SHIFT 0 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) #define OMAP24XX_APLLS_CLKIN_SHIFT 23 +#define OMAP24XX_APLLS_CLKIN_WIDTH 3 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h index 9ad7594e7622..e966e3a3c931 100644 --- a/arch/arm/mach-omap2/cm2_7xx.h +++ b/arch/arm/mach-omap2/cm2_7xx.h @@ -357,6 +357,10 @@ #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 #define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0) +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8 +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8) #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 #define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h index f338177e6900..07c88ae083fb 100644 --- a/arch/arm/mach-omap2/common-board-devices.h +++ b/arch/arm/mach-omap2/common-board-devices.h @@ -1,6 +1,8 @@ #ifndef __OMAP_COMMON_BOARD_DEVICES__ #define __OMAP_COMMON_BOARD_DEVICES__ +#include <sound/tlv320aic3x.h> +#include <linux/mfd/menelaus.h> #include "twl-common.h" #define NAND_BLOCK_SIZE SZ_128K @@ -12,4 +14,7 @@ void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, struct ads7846_platform_data *board_pdata); void *n8x0_legacy_init(void); +extern struct menelaus_platform_data n8x0_menelaus_platform_data; +extern struct aic3x_pdata n810_aic33_data; + #endif /* __OMAP_COMMON_BOARD_DEVICES__ */ diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index dc571f1d3b8a..377eea849e7b 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -32,6 +32,7 @@ #include <linux/i2c/twl.h> #include <linux/i2c-omap.h> #include <linux/reboot.h> +#include <linux/irqchip/irq-omap-intc.h> #include <asm/proc-fns.h> @@ -60,7 +61,7 @@ static inline int omap3_pm_init(void) } #endif -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) +#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)) int omap4_pm_init(void); int omap4_pm_init_early(void); #else @@ -210,18 +211,6 @@ extern struct device *omap2_get_iva_device(void); extern struct device *omap2_get_l3_device(void); extern struct device *omap4_get_dsp_device(void); -void omap2_init_irq(void); -void omap3_init_irq(void); -void ti81xx_init_irq(void); -extern int omap_irq_pending(void); -void omap_intc_save_context(void); -void omap_intc_restore_context(void); -void omap3_intc_suspend(void); -void omap3_intc_prepare_idle(void); -void omap3_intc_resume_idle(void); -void omap2_intc_handle_irq(struct pt_regs *regs); -void omap3_intc_handle_irq(struct pt_regs *regs); -void omap_intc_of_init(void); void omap_gic_of_init(void); #ifdef CONFIG_CACHE_L2X0 @@ -229,16 +218,6 @@ extern void __iomem *omap4_get_l2cache_base(void); #endif struct device_node; -#ifdef CONFIG_OF -int __init intc_of_init(struct device_node *node, - struct device_node *parent); -#else -int __init intc_of_init(struct device_node *node, - struct device_node *parent) -{ - return 0; -} -#endif #ifdef CONFIG_SMP extern void __iomem *omap4_get_scu_base(void); @@ -307,7 +286,7 @@ static inline void omap4_cpu_resume(void) #endif -void pdata_quirks_init(struct of_device_id *); +void pdata_quirks_init(const struct of_device_id *); void omap_auxdata_legacy_init(struct device *dev); void omap_pcs_legacy_init(int irq, void (*rearm)(void)); diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 751f3549bf6f..da041b4ab29c 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -44,8 +44,7 @@ struct omap3_scratchpad { }; struct omap3_scratchpad_prcm_block { - u32 prm_clksrc_ctrl; - u32 prm_clksel; + u32 prm_contents[2]; u32 cm_contents[11]; u32 prcm_block_size; }; @@ -281,14 +280,11 @@ void omap3_clear_scratchpad_contents(void) u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; void __iomem *v_addr; u32 offset = 0; + v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); - if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & - OMAP3430_GLOBAL_COLD_RST_MASK) { + if (omap3xxx_prm_clear_global_cold_reset()) { for ( ; offset <= max_offset; offset += 0x4) writel_relaxed(0x0, (v_addr + offset)); - omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, - OMAP3430_GR_MOD, - OMAP3_PRM_RSTST_OFFSET); } } @@ -314,7 +310,8 @@ void omap3_save_scratchpad_contents(void) scratchpad_contents.public_restore_ptr = virt_to_phys(omap3_restore_3630); else if (omap_rev() != OMAP3430_REV_ES3_0 && - omap_rev() != OMAP3430_REV_ES3_1) + omap_rev() != OMAP3430_REV_ES3_1 && + omap_rev() != OMAP3430_REV_ES3_1_2) scratchpad_contents.public_restore_ptr = virt_to_phys(omap3_restore); else @@ -331,13 +328,7 @@ void omap3_save_scratchpad_contents(void) scratchpad_contents.sdrc_block_offset = 0x64; /* Populate the PRCM block contents */ - prcm_block_contents.prm_clksrc_ctrl = - omap2_prm_read_mod_reg(OMAP3430_GR_MOD, - OMAP3_PRM_CLKSRC_CTRL_OFFSET); - prcm_block_contents.prm_clksel = - omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, - OMAP3_PRM_CLKSEL_OFFSET); - + omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); prcm_block_contents.prcm_block_size = 0x0; @@ -474,7 +465,6 @@ void omap3_control_save_context(void) control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); control_context.padconf_sys_nirq = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); - return; } void omap3_control_restore_context(void) @@ -532,7 +522,6 @@ void omap3_control_restore_context(void) omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); omap_ctrl_writel(control_context.padconf_sys_nirq, OMAP343X_CONTROL_PADCONF_SYSNIRQ); - return; } void omap3630_ctrl_disable_rta(void) @@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void) * Sets the bootmode for IVA2 to idle. This is needed by the PM code to * force disable IVA2 so that it does not prevent any low-power states. */ -void omap3_ctrl_set_iva_bootmode_idle(void) +static void __init omap3_ctrl_set_iva_bootmode_idle(void) { omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, OMAP343X_CONTROL_IVA2_BOOTMOD); } + +/** + * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle + * + * Sets up the pads controlling the stacked modem in such way that the + * device can enter idle. + */ +static void __init omap3_ctrl_setup_d2d_padconf(void) +{ + u16 mask, padconf; + + /* + * In a stand alone OMAP3430 where there is not a stacked + * modem for the D2D Idle Ack and D2D MStandby must be pulled + * high. S CONTROL_PADCONF_SAD2D_IDLEACK and + * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. + */ + mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ + padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); + padconf |= mask; + omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); + + padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); + padconf |= mask; + omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); +} + +/** + * omap3_ctrl_init - does static initializations for control module + * + * Initializes system control module. This sets up the sysconfig autoidle, + * and sets up modem and iva2 so that they can be idled properly. + */ +void __init omap3_ctrl_init(void) +{ + omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); + + omap3_ctrl_set_iva_bootmode_idle(); + + omap3_ctrl_setup_d2d_padconf(); +} #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index da054801b114..a3c013345c45 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -16,11 +16,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H #define __ARCH_ARM_MACH_OMAP2_CONTROL_H -#include "ctrl_module_core_44xx.h" -#include "ctrl_module_wkup_44xx.h" -#include "ctrl_module_pad_core_44xx.h" -#include "ctrl_module_pad_wkup_44xx.h" - #include "am33xx.h" #ifndef __ASSEMBLY__ @@ -254,6 +249,39 @@ /* TI81XX CONTROL_DEVCONF register offsets */ #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) +/* OMAP4 CONTROL MODULE */ +#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 +#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 +#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 + +/* OMAP4 CONTROL_DSIPHY */ +#define OMAP4_DSI2_LANEENABLE_SHIFT 29 +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) +#define OMAP4_DSI1_LANEENABLE_SHIFT 24 +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_DSI1_PIPD_SHIFT 19 +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) +#define OMAP4_DSI2_PIPD_SHIFT 14 +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) + +/* OMAP4 CONTROL_CAMERA_RX */ +#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 +#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 +#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) +#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 +#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) +#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 +#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) + /* OMAP54XX CONTROL STATUS register */ #define OMAP5XXX_CONTROL_STATUS 0x134 #define OMAP5_DEVICETYPE_MASK (0x7 << 6) @@ -427,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); -extern void omap3_ctrl_set_iva_bootmode_idle(void); +void omap3_ctrl_init(void); extern void omap2_set_globals_control(void __iomem *ctrl, void __iomem *ctrl_pad); #else diff --git a/arch/arm/mach-omap2/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h deleted file mode 100644 index 01970824e0e5..000000000000 --- a/arch/arm/mach-omap2/ctrl_module_core_44xx.h +++ /dev/null @@ -1,392 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_CORE registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_CORE 0x4a002000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 -#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 -#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 -#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 -#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 -#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 -#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 -#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 -#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 -#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 -#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c -#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 -#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 -#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 -#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 -#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 -#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 -#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* STD_FUSE_DIE_ID_0 */ -#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) - -/* ID_CODE */ -#define OMAP4_STD_FUSE_IDCODE_SHIFT 0 -#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_1 */ -#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_2 */ -#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) - -/* STD_FUSE_DIE_ID_3 */ -#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 -#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) - -/* STD_FUSE_PROD_ID_0 */ -#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 -#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) - -/* STD_FUSE_PROD_ID_1 */ -#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 -#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) - -/* STD_FUSE_USB_CONF */ -#define OMAP4_USB_PROD_ID_SHIFT 16 -#define OMAP4_USB_PROD_ID_MASK (0xffff << 16) -#define OMAP4_USB_VENDOR_ID_SHIFT 0 -#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) - -/* STD_FUSE_OPP_VDD_WKUP */ -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_BGAP */ -#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_DPLL_0 */ -#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) - -/* STD_FUSE_OPP_DPLL_1 */ -#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 -#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) - -/* STATUS */ -#define OMAP4_ATTILA_CONF_SHIFT 11 -#define OMAP4_ATTILA_CONF_MASK (0x3 << 11) -#define OMAP4_DEVICE_TYPE_SHIFT 8 -#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) -#define OMAP4_SYS_BOOT_SHIFT 0 -#define OMAP4_SYS_BOOT_MASK (0xff << 0) - -/* DEV_CONF */ -#define OMAP4_DEV_CONF_SHIFT 1 -#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) -#define OMAP4_USBPHY_PD_SHIFT 0 -#define OMAP4_USBPHY_PD_MASK (1 << 0) - -/* LDOVBB_IVA_VOLTAGE_CTRL */ -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 -#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 -#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 -#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 -#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) - -/* LDOVBB_MPU_VOLTAGE_CTRL */ -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 -#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 -#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 -#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 -#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_IVA_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_MPU_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* LDOSRAM_CORE_VOLTAGE_CTRL */ -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 -#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 -#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 -#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 -#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) - -/* TEMP_SENSOR */ -#define OMAP4_BGAP_TEMPSOFF_SHIFT 12 -#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) -#define OMAP4_BGAP_TSHUT_SHIFT 11 -#define OMAP4_BGAP_TSHUT_MASK (1 << 11) -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) -#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 -#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) - -/* DPLL_NWELL_TRIM_0 */ -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 -#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) -#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 -#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 -#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) -#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 -#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 -#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) -#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 -#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 -#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) -#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 -#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 -#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) -#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 -#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) - -/* DPLL_NWELL_TRIM_1 */ -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 -#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 -#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) -#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 -#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) -#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 -#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) -#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 -#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) -#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 -#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) - -/* USBOTGHS_CONTROL */ -#define OMAP4_DISCHRGVBUS_SHIFT 8 -#define OMAP4_DISCHRGVBUS_MASK (1 << 8) -#define OMAP4_CHRGVBUS_SHIFT 7 -#define OMAP4_CHRGVBUS_MASK (1 << 7) -#define OMAP4_DRVVBUS_SHIFT 6 -#define OMAP4_DRVVBUS_MASK (1 << 6) -#define OMAP4_IDPULLUP_SHIFT 5 -#define OMAP4_IDPULLUP_MASK (1 << 5) -#define OMAP4_IDDIG_SHIFT 4 -#define OMAP4_IDDIG_MASK (1 << 4) -#define OMAP4_SESSEND_SHIFT 3 -#define OMAP4_SESSEND_MASK (1 << 3) -#define OMAP4_VBUSVALID_SHIFT 2 -#define OMAP4_VBUSVALID_MASK (1 << 2) -#define OMAP4_BVALID_SHIFT 1 -#define OMAP4_BVALID_MASK (1 << 1) -#define OMAP4_AVALID_SHIFT 0 -#define OMAP4_AVALID_MASK (1 << 0) - -/* DSS_CONTROL */ -#define OMAP4_DSS_MUX6_SELECT_SHIFT 0 -#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) - -/* HWOBS_CONTROL */ -#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 -#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) -#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 -#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) -#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 -#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) -#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 -#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) - -/* DEBOBS_FINAL_MUX_SEL */ -#define OMAP4_SELECT_SHIFT 0 -#define OMAP4_SELECT_MASK (0xffffffff << 0) - -/* DEBOBS_MMR_MPU */ -#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 -#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) - -/* CONF_SDMA_REQ_SEL0 */ -#define OMAP4_MULT_SHIFT 0 -#define OMAP4_MULT_MASK (0x7f << 0) - -/* CONF_CLK_SEL0 */ -#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) - -/* CONF_CLK_SEL1 */ -#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) - -/* CONF_CLK_SEL2 */ -#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 -#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) - -/* CONF_DPLL_FREQLOCK_SEL */ -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) - -/* CONF_DPLL_TINITZ_SEL */ -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) - -/* CONF_DPLL_PHASELOCK_SEL */ -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 -#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) - -/* CONF_DEBUG_SEL_TST_0 */ -#define OMAP4_MODE_SHIFT 0 -#define OMAP4_MODE_MASK (0xf << 0) - -#endif diff --git a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h deleted file mode 100644 index c88420de1151..000000000000 --- a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h +++ /dev/null @@ -1,1409 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec -#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 -#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 -#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* PADCONF_WAKEUPEVENT_0 */ -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_1 */ -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_2 */ -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_3 */ -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_4 */ -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_5 */ -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 -#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 -#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 -#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 -#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 -#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 -#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 -#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* PADCONF_WAKEUPEVENT_6 */ -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* CONTROL_PADCONF_GLOBAL */ -#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 -#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) - -/* CONTROL_PADCONF_MODE */ -#define OMAP4_VDDS_DV_BANK0_SHIFT 31 -#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) -#define OMAP4_VDDS_DV_BANK1_SHIFT 30 -#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) -#define OMAP4_VDDS_DV_BANK3_SHIFT 29 -#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) -#define OMAP4_VDDS_DV_BANK4_SHIFT 28 -#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) -#define OMAP4_VDDS_DV_BANK5_SHIFT 27 -#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) -#define OMAP4_VDDS_DV_BANK6_SHIFT 26 -#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) -#define OMAP4_VDDS_DV_C2C_SHIFT 25 -#define OMAP4_VDDS_DV_C2C_MASK (1 << 25) -#define OMAP4_VDDS_DV_CAM_SHIFT 24 -#define OMAP4_VDDS_DV_CAM_MASK (1 << 24) -#define OMAP4_VDDS_DV_GPMC_SHIFT 23 -#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) -#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 -#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) - -/* CONTROL_SMART1IO_PADCONF_0 */ -#define OMAP4_ABE_DR0_SC_SHIFT 30 -#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) -#define OMAP4_CAM_DR0_SC_SHIFT 28 -#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) -#define OMAP4_FREF_DR2_SC_SHIFT 26 -#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) -#define OMAP4_FREF_DR3_SC_SHIFT 24 -#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) -#define OMAP4_GPIO_DR8_SC_SHIFT 22 -#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) -#define OMAP4_GPIO_DR9_SC_SHIFT 20 -#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) -#define OMAP4_GPMC_DR2_SC_SHIFT 18 -#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) -#define OMAP4_GPMC_DR3_SC_SHIFT 16 -#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) -#define OMAP4_GPMC_DR6_SC_SHIFT 14 -#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) -#define OMAP4_HDMI_DR0_SC_SHIFT 12 -#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) -#define OMAP4_MCSPI1_DR0_SC_SHIFT 10 -#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) -#define OMAP4_UART1_DR0_SC_SHIFT 8 -#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) -#define OMAP4_UART3_DR0_SC_SHIFT 6 -#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) -#define OMAP4_UART3_DR1_SC_SHIFT 4 -#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) -#define OMAP4_UNIPRO_DR0_SC_SHIFT 2 -#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) -#define OMAP4_UNIPRO_DR1_SC_SHIFT 0 -#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) - -/* CONTROL_SMART1IO_PADCONF_1 */ -#define OMAP4_ABE_DR0_LB_SHIFT 30 -#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) -#define OMAP4_CAM_DR0_LB_SHIFT 28 -#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) -#define OMAP4_FREF_DR2_LB_SHIFT 26 -#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) -#define OMAP4_FREF_DR3_LB_SHIFT 24 -#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) -#define OMAP4_GPIO_DR8_LB_SHIFT 22 -#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) -#define OMAP4_GPIO_DR9_LB_SHIFT 20 -#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) -#define OMAP4_GPMC_DR2_LB_SHIFT 18 -#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) -#define OMAP4_GPMC_DR3_LB_SHIFT 16 -#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) -#define OMAP4_GPMC_DR6_LB_SHIFT 14 -#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) -#define OMAP4_HDMI_DR0_LB_SHIFT 12 -#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) -#define OMAP4_MCSPI1_DR0_LB_SHIFT 10 -#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) -#define OMAP4_UART1_DR0_LB_SHIFT 8 -#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) -#define OMAP4_UART3_DR0_LB_SHIFT 6 -#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) -#define OMAP4_UART3_DR1_LB_SHIFT 4 -#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) -#define OMAP4_UNIPRO_DR0_LB_SHIFT 2 -#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) -#define OMAP4_UNIPRO_DR1_LB_SHIFT 0 -#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) - -/* CONTROL_SMART2IO_PADCONF_0 */ -#define OMAP4_C2C_DR0_LB_SHIFT 31 -#define OMAP4_C2C_DR0_LB_MASK (1 << 31) -#define OMAP4_DPM_DR1_LB_SHIFT 30 -#define OMAP4_DPM_DR1_LB_MASK (1 << 30) -#define OMAP4_DPM_DR2_LB_SHIFT 29 -#define OMAP4_DPM_DR2_LB_MASK (1 << 29) -#define OMAP4_DPM_DR3_LB_SHIFT 28 -#define OMAP4_DPM_DR3_LB_MASK (1 << 28) -#define OMAP4_GPIO_DR0_LB_SHIFT 27 -#define OMAP4_GPIO_DR0_LB_MASK (1 << 27) -#define OMAP4_GPIO_DR1_LB_SHIFT 26 -#define OMAP4_GPIO_DR1_LB_MASK (1 << 26) -#define OMAP4_GPIO_DR10_LB_SHIFT 25 -#define OMAP4_GPIO_DR10_LB_MASK (1 << 25) -#define OMAP4_GPIO_DR2_LB_SHIFT 24 -#define OMAP4_GPIO_DR2_LB_MASK (1 << 24) -#define OMAP4_GPMC_DR0_LB_SHIFT 23 -#define OMAP4_GPMC_DR0_LB_MASK (1 << 23) -#define OMAP4_GPMC_DR1_LB_SHIFT 22 -#define OMAP4_GPMC_DR1_LB_MASK (1 << 22) -#define OMAP4_GPMC_DR4_LB_SHIFT 21 -#define OMAP4_GPMC_DR4_LB_MASK (1 << 21) -#define OMAP4_GPMC_DR5_LB_SHIFT 20 -#define OMAP4_GPMC_DR5_LB_MASK (1 << 20) -#define OMAP4_GPMC_DR7_LB_SHIFT 19 -#define OMAP4_GPMC_DR7_LB_MASK (1 << 19) -#define OMAP4_HSI2_DR0_LB_SHIFT 18 -#define OMAP4_HSI2_DR0_LB_MASK (1 << 18) -#define OMAP4_HSI2_DR1_LB_SHIFT 17 -#define OMAP4_HSI2_DR1_LB_MASK (1 << 17) -#define OMAP4_HSI2_DR2_LB_SHIFT 16 -#define OMAP4_HSI2_DR2_LB_MASK (1 << 16) -#define OMAP4_KPD_DR0_LB_SHIFT 15 -#define OMAP4_KPD_DR0_LB_MASK (1 << 15) -#define OMAP4_KPD_DR1_LB_SHIFT 14 -#define OMAP4_KPD_DR1_LB_MASK (1 << 14) -#define OMAP4_PDM_DR0_LB_SHIFT 13 -#define OMAP4_PDM_DR0_LB_MASK (1 << 13) -#define OMAP4_SDMMC2_DR0_LB_SHIFT 12 -#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) -#define OMAP4_SDMMC3_DR0_LB_SHIFT 11 -#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) -#define OMAP4_SDMMC4_DR0_LB_SHIFT 10 -#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) -#define OMAP4_SDMMC4_DR1_LB_SHIFT 9 -#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) -#define OMAP4_SPI3_DR0_LB_SHIFT 8 -#define OMAP4_SPI3_DR0_LB_MASK (1 << 8) -#define OMAP4_SPI3_DR1_LB_SHIFT 7 -#define OMAP4_SPI3_DR1_LB_MASK (1 << 7) -#define OMAP4_UART3_DR2_LB_SHIFT 6 -#define OMAP4_UART3_DR2_LB_MASK (1 << 6) -#define OMAP4_UART3_DR3_LB_SHIFT 5 -#define OMAP4_UART3_DR3_LB_MASK (1 << 5) -#define OMAP4_UART3_DR4_LB_SHIFT 4 -#define OMAP4_UART3_DR4_LB_MASK (1 << 4) -#define OMAP4_UART3_DR5_LB_SHIFT 3 -#define OMAP4_UART3_DR5_LB_MASK (1 << 3) -#define OMAP4_USBA0_DR1_LB_SHIFT 2 -#define OMAP4_USBA0_DR1_LB_MASK (1 << 2) -#define OMAP4_USBA_DR2_LB_SHIFT 1 -#define OMAP4_USBA_DR2_LB_MASK (1 << 1) - -/* CONTROL_SMART2IO_PADCONF_1 */ -#define OMAP4_USBB1_DR0_LB_SHIFT 31 -#define OMAP4_USBB1_DR0_LB_MASK (1 << 31) -#define OMAP4_USBB2_DR0_LB_SHIFT 30 -#define OMAP4_USBB2_DR0_LB_MASK (1 << 30) -#define OMAP4_USBA0_DR0_LB_SHIFT 29 -#define OMAP4_USBA0_DR0_LB_MASK (1 << 29) - -/* CONTROL_SMART3IO_PADCONF_0 */ -#define OMAP4_DMIC_DR0_MB_SHIFT 30 -#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) -#define OMAP4_GPIO_DR3_MB_SHIFT 28 -#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) -#define OMAP4_GPIO_DR4_MB_SHIFT 26 -#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) -#define OMAP4_GPIO_DR5_MB_SHIFT 24 -#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) -#define OMAP4_GPIO_DR6_MB_SHIFT 22 -#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) -#define OMAP4_HSI_DR1_MB_SHIFT 20 -#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) -#define OMAP4_HSI_DR2_MB_SHIFT 18 -#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) -#define OMAP4_HSI_DR3_MB_SHIFT 16 -#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) -#define OMAP4_MCBSP2_DR0_MB_SHIFT 14 -#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) -#define OMAP4_MCSPI4_DR0_MB_SHIFT 12 -#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) -#define OMAP4_MCSPI4_DR1_MB_SHIFT 10 -#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) -#define OMAP4_SDMMC3_DR0_MB_SHIFT 8 -#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) -#define OMAP4_SPI2_DR0_MB_SHIFT 0 -#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) - -/* CONTROL_SMART3IO_PADCONF_1 */ -#define OMAP4_SPI2_DR1_MB_SHIFT 30 -#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) -#define OMAP4_SPI2_DR2_MB_SHIFT 28 -#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) -#define OMAP4_UART2_DR0_MB_SHIFT 26 -#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) -#define OMAP4_UART2_DR1_MB_SHIFT 24 -#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) -#define OMAP4_UART4_DR0_MB_SHIFT 22 -#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) -#define OMAP4_HSI_DR0_MB_SHIFT 20 -#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) - -/* CONTROL_SMART3IO_PADCONF_2 */ -#define OMAP4_DMIC_DR0_LB_SHIFT 31 -#define OMAP4_DMIC_DR0_LB_MASK (1 << 31) -#define OMAP4_GPIO_DR3_LB_SHIFT 30 -#define OMAP4_GPIO_DR3_LB_MASK (1 << 30) -#define OMAP4_GPIO_DR4_LB_SHIFT 29 -#define OMAP4_GPIO_DR4_LB_MASK (1 << 29) -#define OMAP4_GPIO_DR5_LB_SHIFT 28 -#define OMAP4_GPIO_DR5_LB_MASK (1 << 28) -#define OMAP4_GPIO_DR6_LB_SHIFT 27 -#define OMAP4_GPIO_DR6_LB_MASK (1 << 27) -#define OMAP4_HSI_DR1_LB_SHIFT 26 -#define OMAP4_HSI_DR1_LB_MASK (1 << 26) -#define OMAP4_HSI_DR2_LB_SHIFT 25 -#define OMAP4_HSI_DR2_LB_MASK (1 << 25) -#define OMAP4_HSI_DR3_LB_SHIFT 24 -#define OMAP4_HSI_DR3_LB_MASK (1 << 24) -#define OMAP4_MCBSP2_DR0_LB_SHIFT 23 -#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) -#define OMAP4_MCSPI4_DR0_LB_SHIFT 22 -#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) -#define OMAP4_MCSPI4_DR1_LB_SHIFT 21 -#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) -#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 -#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) -#define OMAP4_SPI2_DR0_LB_SHIFT 16 -#define OMAP4_SPI2_DR0_LB_MASK (1 << 16) -#define OMAP4_SPI2_DR1_LB_SHIFT 15 -#define OMAP4_SPI2_DR1_LB_MASK (1 << 15) -#define OMAP4_SPI2_DR2_LB_SHIFT 14 -#define OMAP4_SPI2_DR2_LB_MASK (1 << 14) -#define OMAP4_UART2_DR0_LB_SHIFT 13 -#define OMAP4_UART2_DR0_LB_MASK (1 << 13) -#define OMAP4_UART2_DR1_LB_SHIFT 12 -#define OMAP4_UART2_DR1_LB_MASK (1 << 12) -#define OMAP4_UART4_DR0_LB_SHIFT 11 -#define OMAP4_UART4_DR0_LB_MASK (1 << 11) -#define OMAP4_HSI_DR0_LB_SHIFT 10 -#define OMAP4_HSI_DR0_LB_MASK (1 << 10) - -/* CONTROL_USBB_HSIC */ -#define OMAP4_USBB2_DR1_SR_SHIFT 30 -#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) -#define OMAP4_USBB2_DR1_I_SHIFT 27 -#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) -#define OMAP4_USBB1_DR1_SR_SHIFT 25 -#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) -#define OMAP4_USBB1_DR1_I_SHIFT 22 -#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) -#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 -#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) -#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 -#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) -#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 -#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) -#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 -#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 -#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 -#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 -#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 -#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) - -/* CONTROL_SLIMBUS */ -#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 -#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) -#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 -#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) -#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 -#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) -#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 -#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) -#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 -#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) -#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 -#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) -#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 -#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) -#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 -#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) - -/* CONTROL_PBIASLITE */ -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 -#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 -#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 -#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) -#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 -#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) -#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 -#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) -#define OMAP4_MMC1_PWRDNZ_SHIFT 26 -#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 -#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) -#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 -#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) -#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 -#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) - -/* CONTROL_I2C_0 */ -#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 -#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 -#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) -#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 -#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 -#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) -#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 -#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) -#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 -#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) -#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 -#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) -#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 -#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) -#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 -#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) -#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 -#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) -#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 -#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) -#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 -#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) -#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 -#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) -#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 -#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) -#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 -#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) -#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 -#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) -#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 -#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) -#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 -#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) -#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 -#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) -#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 -#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) -#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 -#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) -#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 -#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) - -/* CONTROL_CAMERA_RX */ -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 -#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) -#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 -#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) -#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 -#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 -#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 -#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) -#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 -#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 -#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) -#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 -#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) - -/* CONTROL_AVDAC */ -#define OMAP4_AVDAC_ACEN_SHIFT 31 -#define OMAP4_AVDAC_ACEN_MASK (1 << 31) -#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 -#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) -#define OMAP4_AVDAC_INPUTINV_SHIFT 29 -#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) -#define OMAP4_AVDAC_CTL_SHIFT 13 -#define OMAP4_AVDAC_CTL_MASK (0xffff << 13) -#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 -#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) - -/* CONTROL_HDMI_TX_PHY */ -#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 -#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) -#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 -#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) -#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 -#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) -#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 -#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) - -/* CONTROL_MMC2 */ -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 -#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) - -/* CONTROL_DSIPHY */ -#define OMAP4_DSI2_LANEENABLE_SHIFT 29 -#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) -#define OMAP4_DSI1_LANEENABLE_SHIFT 24 -#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) -#define OMAP4_DSI1_PIPD_SHIFT 19 -#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) -#define OMAP4_DSI2_PIPD_SHIFT 14 -#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) - -/* CONTROL_MCBSPLP */ -#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 -#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) -#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 -#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) -#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 -#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) - -/* CONTROL_USB2PHYCORE */ -#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 -#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) -#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 -#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) -#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 -#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 -#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 -#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 -#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) -#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 -#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) -#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 -#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) -#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 -#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 -#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 -#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) -#define OMAP4_USB2PHY_DATADET_SHIFT 18 -#define OMAP4_USB2PHY_DATADET_MASK (1 << 18) -#define OMAP4_USB2PHY_SINKONDP_SHIFT 17 -#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) -#define OMAP4_USB2PHY_SRCONDM_SHIFT 16 -#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) -#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 -#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) -#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 -#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) -#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 -#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) -#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 -#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) -#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 -#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) -#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 -#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) -#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 -#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 -#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) -#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 -#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) -#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 -#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) -#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 -#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) - -/* CONTROL_I2C_1 */ -#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 -#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 -#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 -#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 -#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) -#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 -#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) -#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 -#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) -#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 -#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) -#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 -#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) - -/* CONTROL_MMC1 */ -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 -#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 -#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 -#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 -#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) -#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 -#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) -#define OMAP4_USB_FD_CDEN_SHIFT 23 -#define OMAP4_USB_FD_CDEN_MASK (1 << 23) -#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 -#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) -#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 -#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) - -/* CONTROL_HSI */ -#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 -#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) -#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 -#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) -#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 -#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) -#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 -#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) - -/* CONTROL_USB */ -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 -#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) - -/* CONTROL_HDQ */ -#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 -#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) - -/* CONTROL_LPDDR2IO1_0 */ -#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 -#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 -#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 -#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO1_1 */ -#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 -#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 -#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 -#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO1_2 */ -#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 -#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 -#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 -#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 -#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 -#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 -#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 -#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 -#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 -#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) - -/* CONTROL_LPDDR2IO1_3 */ -#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 -#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) -#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 -#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 -#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 -#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 -#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) -#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 -#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) -#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 -#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 -#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 -#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 -#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 -#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 -#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 -#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) -#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 -#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) -#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 -#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) - -/* CONTROL_LPDDR2IO2_0 */ -#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 -#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 -#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 -#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO2_1 */ -#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) -#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 -#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) -#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 -#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) -#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 -#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) - -/* CONTROL_LPDDR2IO2_2 */ -#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 -#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) -#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 -#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) -#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 -#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) -#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 -#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) -#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 -#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) -#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 -#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) -#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 -#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) -#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 -#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) -#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 -#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) - -/* CONTROL_LPDDR2IO2_3 */ -#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 -#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) -#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 -#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 -#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 -#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 -#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) -#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 -#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) -#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 -#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 -#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 -#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 -#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 -#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 -#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 -#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) -#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 -#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) -#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 -#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) - -/* CONTROL_BUS_HOLD */ -#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 -#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) -#define OMAP4_MCSPI1_CS3_EN_SHIFT 30 -#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) - -/* CONTROL_C2C */ -#define OMAP4_MIRROR_MODE_EN_SHIFT 31 -#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) -#define OMAP4_C2C_SPARE_SHIFT 24 -#define OMAP4_C2C_SPARE_MASK (0x7f << 24) - -/* CORE_CONTROL_SPARE_RW */ -#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 -#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) - -/* CORE_CONTROL_SPARE_R */ -#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 -#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) - -/* CORE_CONTROL_SPARE_R_C0 */ -#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 -#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) -#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 -#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) -#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 -#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) -#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 -#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) -#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 -#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) -#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 -#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) -#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 -#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) -#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 -#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) - -/* CONTROL_EFUSE_1 */ -#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 -#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) -#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 -#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) -#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 -#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) -#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 -#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) - -/* CONTROL_EFUSE_2 */ -#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 -#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) -#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 -#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) -#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 -#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) -#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 -#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) -#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 -#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) -#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 -#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) -#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 -#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) -#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 -#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) -#define OMAP4_LPDDR2_PTV_N1_SHIFT 23 -#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) -#define OMAP4_LPDDR2_PTV_N2_SHIFT 22 -#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) -#define OMAP4_LPDDR2_PTV_N3_SHIFT 21 -#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) -#define OMAP4_LPDDR2_PTV_N4_SHIFT 20 -#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) -#define OMAP4_LPDDR2_PTV_N5_SHIFT 19 -#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) -#define OMAP4_LPDDR2_PTV_P1_SHIFT 18 -#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) -#define OMAP4_LPDDR2_PTV_P2_SHIFT 17 -#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) -#define OMAP4_LPDDR2_PTV_P3_SHIFT 16 -#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) -#define OMAP4_LPDDR2_PTV_P4_SHIFT 15 -#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) -#define OMAP4_LPDDR2_PTV_P5_SHIFT 14 -#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) - -/* CONTROL_EFUSE_3 */ -#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 -#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) -#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 -#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) -#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 -#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) -#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 -#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) - -/* CONTROL_EFUSE_4 */ -#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 -#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) -#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 -#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) -#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 -#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) -#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 -#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) - -#endif diff --git a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h deleted file mode 100644 index 17c9b37042c0..000000000000 --- a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H - - -/* Base address */ -#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 - -/* Registers offset */ -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 -#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 -#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 -#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 -#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c - -/* Registers shifts and masks */ - -/* IP_REVISION */ -#define OMAP4_IP_REV_SCHEME_SHIFT 30 -#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) -#define OMAP4_IP_REV_FUNC_SHIFT 16 -#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) -#define OMAP4_IP_REV_RTL_SHIFT 11 -#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) -#define OMAP4_IP_REV_MAJOR_SHIFT 8 -#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) -#define OMAP4_IP_REV_CUSTOM_SHIFT 6 -#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) -#define OMAP4_IP_REV_MINOR_SHIFT 0 -#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) - -/* IP_HWINFO */ -#define OMAP4_IP_HWINFO_SHIFT 0 -#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) - -/* IP_SYSCONFIG */ -#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 -#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) - -/* PADCONF_WAKEUPEVENT_0 */ -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 -#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 -#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 -#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 -#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 -#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 -#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 -#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 -#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 -#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 -#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 -#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 -#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 -#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 -#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 -#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 -#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 -#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 -#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 -#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 -#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 -#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 -#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 -#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 -#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 -#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) - -/* CONTROL_SMART1NOPMIO_PADCONF_0 */ -#define OMAP4_FREF_DR0_SC_SHIFT 30 -#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) -#define OMAP4_FREF_DR1_SC_SHIFT 28 -#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) -#define OMAP4_FREF_DR4_SC_SHIFT 26 -#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) -#define OMAP4_FREF_DR5_SC_SHIFT 24 -#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) -#define OMAP4_FREF_DR6_SC_SHIFT 22 -#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) -#define OMAP4_FREF_DR7_SC_SHIFT 20 -#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) -#define OMAP4_GPIO_DR7_SC_SHIFT 18 -#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) -#define OMAP4_DPM_DR0_SC_SHIFT 14 -#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) -#define OMAP4_SIM_DR0_SC_SHIFT 12 -#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) - -/* CONTROL_SMART1NOPMIO_PADCONF_1 */ -#define OMAP4_FREF_DR0_LB_SHIFT 30 -#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) -#define OMAP4_FREF_DR1_LB_SHIFT 28 -#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) -#define OMAP4_FREF_DR4_LB_SHIFT 26 -#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) -#define OMAP4_FREF_DR5_LB_SHIFT 24 -#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) -#define OMAP4_FREF_DR6_LB_SHIFT 22 -#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) -#define OMAP4_FREF_DR7_LB_SHIFT 20 -#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) -#define OMAP4_GPIO_DR7_LB_SHIFT 18 -#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) -#define OMAP4_DPM_DR0_LB_SHIFT 14 -#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) -#define OMAP4_SIM_DR0_LB_SHIFT 12 -#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) - -/* CONTROL_PADCONF_MODE */ -#define OMAP4_VDDS_DV_FREF_SHIFT 31 -#define OMAP4_VDDS_DV_FREF_MASK (1 << 31) -#define OMAP4_VDDS_DV_BANK2_SHIFT 30 -#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) - -/* CONTROL_XTAL_OSCILLATOR */ -#define OMAP4_OSCILLATOR_BOOST_SHIFT 31 -#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) -#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 -#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) - -/* CONTROL_USIMIO */ -#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 -#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) -#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 -#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) -#define OMAP4_USIM_PWRDNZ_SHIFT 28 -#define OMAP4_USIM_PWRDNZ_MASK (1 << 28) - -/* CONTROL_I2C_2 */ -#define OMAP4_SR_SDA_GLFENB_SHIFT 31 -#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) -#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 -#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) -#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 -#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) -#define OMAP4_SR_SCL_GLFENB_SHIFT 27 -#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) -#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 -#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) -#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 -#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) - -/* CONTROL_JTAG */ -#define OMAP4_JTAG_NTRST_EN_SHIFT 31 -#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) -#define OMAP4_JTAG_TCK_EN_SHIFT 30 -#define OMAP4_JTAG_TCK_EN_MASK (1 << 30) -#define OMAP4_JTAG_RTCK_EN_SHIFT 29 -#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) -#define OMAP4_JTAG_TDI_EN_SHIFT 28 -#define OMAP4_JTAG_TDI_EN_MASK (1 << 28) -#define OMAP4_JTAG_TDO_EN_SHIFT 27 -#define OMAP4_JTAG_TDO_EN_MASK (1 << 27) - -/* CONTROL_SYS */ -#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 -#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) - -/* WKUP_CONTROL_SPARE_RW */ -#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 -#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) - -/* WKUP_CONTROL_SPARE_R */ -#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 -#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) - -/* WKUP_CONTROL_SPARE_R_C0 */ -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 -#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 -#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 -#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 -#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 -#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 -#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 -#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 -#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) - -#endif diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index b6f8f348296e..324f02bf8a51 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -432,9 +432,9 @@ static int __init omap2_init_devices(void) */ omap_init_audio(); omap_init_camera(); - omap_init_mbox(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { + omap_init_mbox(); omap_init_mcspi(); omap_init_sham(); omap_init_aes(); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index bf852d7ae951..7a050f9c37ff 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -544,7 +544,7 @@ int omap_dss_reset(struct omap_hwmod *oh) MAX_MODULE_SOFTRESET_WAIT, c); if (c == MAX_MODULE_SOFTRESET_WAIT) - pr_warning("dss_core: waiting for reset to finish failed\n"); + pr_warn("dss_core: waiting for reset to finish failed\n"); else pr_debug("dss_core: softreset done\n"); diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index a6d2cf1f8d02..e1a56d87599e 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -259,6 +259,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) d->dev_caps |= HS_CHANNELS_RESERVED; + if (platform_get_irq_byname(pdev, "0") < 0) + d->dev_caps |= DMA_ENGINE_HANDLE_IRQ; + /* Check the capabilities register for descriptor loading feature */ if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) dma_common_ch_end = CCDN; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37e2257..ac3d789ac3cd 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -28,11 +28,8 @@ #include <linux/bitops.h> #include <linux/clkdev.h> -#include "soc.h" #include "clockdomain.h" #include "clock.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-34xx.h" /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ #define DPLL_AUTOIDLE_DISABLE 0x0 @@ -310,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) * Set jitter correction. Jitter correction applicable for OMAP343X * only since freqsel field is no longer present on other devices. */ - if (cpu_is_omap343x()) { + if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -478,6 +475,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct clk *new_parent = NULL; + unsigned long rrate; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -505,14 +503,22 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __clk_prepare(dd->clk_ref); clk_enable(dd->clk_ref); - if (dd->last_rounded_rate != rate) - rate = __clk_round_rate(hw->clk, rate); + /* XXX this check is probably pointless in the CCF context */ + if (dd->last_rounded_rate != rate) { + rrate = __clk_round_rate(hw->clk, rate); + if (rrate != rate) { + pr_warn("%s: %s: final rate %lu does not match desired rate %lu\n", + __func__, __clk_get_name(hw->clk), + rrate, rate); + rate = rrate; + } + } if (dd->last_rounded_rate == 0) return -EINVAL; /* Freqsel is available only on OMAP343X devices */ - if (cpu_is_omap343x()) { + if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel); diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 52f9438b92f2..4613f1e86988 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -15,10 +15,7 @@ #include <linux/io.h> #include <linux/bitops.h> -#include "soc.h" #include "clock.h" -#include "clock44xx.h" -#include "cm-regbits-44xx.h" /* * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that @@ -29,13 +26,23 @@ #define OMAP4_DPLL_LP_FINT_MAX 1000000 #define OMAP4_DPLL_LP_FOUT_MAX 100000000 +/* + * Bitfield declarations + */ +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) +#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) + +/* Static rate multiplier for OMAP4 REGM4XEN clocks */ +#define OMAP4430_REGM4XEN_MULT 4 + /* Supported only on OMAP4 */ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) { u32 v; u32 mask; - if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!clk || !clk->clksel_reg) return -EINVAL; mask = clk->flags & CLOCK_CLKOUTX2 ? @@ -54,7 +61,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) u32 v; u32 mask; - if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!clk || !clk->clksel_reg) return; mask = clk->flags & CLOCK_CLKOUTX2 ? @@ -72,7 +79,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) u32 v; u32 mask; - if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!clk || !clk->clksel_reg) return; mask = clk->flags & CLOCK_CLKOUTX2 ? diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 93914d220069..cb7764314f17 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -24,25 +24,6 @@ /* minimum size for IO mapping */ #define NAND_IO_SIZE 4 -static struct resource gpmc_nand_resource[] = { - { - .flags = IORESOURCE_MEM, - }, - { - .flags = IORESOURCE_IRQ, - }, - { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device gpmc_nand_device = { - .name = "omap2-nand", - .id = 0, - .num_resources = ARRAY_SIZE(gpmc_nand_resource), - .resource = gpmc_nand_resource, -}; - static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* platforms which support all ECC schemes */ @@ -68,7 +49,8 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) return 0; /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ - if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) + if (ecc_opt == OMAP_ECC_HAM1_CODE_HW || + ecc_opt == OMAP_ECC_HAM1_CODE_SW) return 1; else return 0; @@ -95,43 +77,41 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, { int err = 0; struct gpmc_settings s; - struct device *dev = &gpmc_nand_device.dev; - - memset(&s, 0, sizeof(struct gpmc_settings)); + struct platform_device *pdev; + struct resource gpmc_nand_res[] = { + { .flags = IORESOURCE_MEM, }, + { .flags = IORESOURCE_IRQ, }, + { .flags = IORESOURCE_IRQ, }, + }; - gpmc_nand_device.dev.platform_data = gpmc_nand_data; + BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM); err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, - (unsigned long *)&gpmc_nand_resource[0].start); + (unsigned long *)&gpmc_nand_res[0].start); if (err < 0) { - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", - gpmc_nand_data->cs, err); + pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n", + gpmc_nand_data->cs, err); return err; } - - gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + - NAND_IO_SIZE - 1; - - gpmc_nand_resource[1].start = - gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); - gpmc_nand_resource[2].start = - gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); + gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1; + gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); + gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); if (gpmc_t) { err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); if (err < 0) { - dev_err(dev, "Unable to set gpmc timings: %d\n", err); + pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err); return err; } } + memset(&s, 0, sizeof(struct gpmc_settings)); if (gpmc_nand_data->of_node) gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); else gpmc_set_legacy(gpmc_nand_data, &s); s.device_nand = true; - err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); if (err < 0) goto out_free_cs; @@ -143,18 +123,34 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { - dev_err(dev, "Unsupported NAND ECC scheme selected\n"); - return -EINVAL; + pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n"); + err = -EINVAL; + goto out_free_cs; } - err = platform_device_register(&gpmc_nand_device); - if (err < 0) { - dev_err(dev, "Unable to register NAND device\n"); - goto out_free_cs; + + pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs); + if (pdev) { + err = platform_device_add_resources(pdev, gpmc_nand_res, + ARRAY_SIZE(gpmc_nand_res)); + if (!err) + pdev->dev.platform_data = gpmc_nand_data; + } else { + err = -ENOMEM; + } + if (err) + goto out_free_pdev; + + err = platform_device_add(pdev); + if (err) { + dev_err(&pdev->dev, "Unable to register NAND device\n"); + goto out_free_pdev; } return 0; +out_free_pdev: + platform_device_put(pdev); out_free_cs: gpmc_cs_free(gpmc_nand_data->cs); diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 8bc13380f0a0..5fa3755261ce 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1207,8 +1207,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) } } - if ((p->wait_on_read || p->wait_on_write) && - (p->wait_pin > gpmc_nr_waitpins)) { + if (p->wait_pin > gpmc_nr_waitpins) { pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); return -EINVAL; } @@ -1244,7 +1243,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) } #ifdef CONFIG_OF -static struct of_device_id gpmc_dt_ids[] = { +static const struct of_device_id gpmc_dt_ids[] = { { .compatible = "ti,omap2420-gpmc" }, { .compatible = "ti,omap2430-gpmc" }, { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ @@ -1288,8 +1287,8 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) p->wait_on_write = of_property_read_bool(np, "gpmc,wait-on-write"); if (!p->wait_on_read && !p->wait_on_write) - pr_warn("%s: read/write wait monitoring not enabled!\n", - __func__); + pr_debug("%s: rd/wr wait monitoring not enabled!\n", + __func__); } } @@ -1403,8 +1402,11 @@ static int gpmc_probe_nand_child(struct platform_device *pdev, pr_err("%s: ti,nand-ecc-opt not found\n", __func__); return -ENODEV; } - if (!strcmp(s, "ham1") || !strcmp(s, "sw") || - !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) + + if (!strcmp(s, "sw")) + gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW; + else if (!strcmp(s, "ham1") || + !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_HW; else if (!strcmp(s, "bch4")) @@ -1438,6 +1440,8 @@ static int gpmc_probe_nand_child(struct platform_device *pdev, break; } + gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child); + val = of_get_nand_bus_width(child); if (val == 16) gpmc_nand_data->devsize = NAND_BUSWIDTH_16; diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index f78b4a161959..f3897d82e53e 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -67,8 +67,8 @@ int omap_hdq1w_reset(struct omap_hwmod *oh) MAX_MODULE_SOFTRESET_WAIT, c); if (c == MAX_MODULE_SOFTRESET_WAIT) - pr_warning("%s: %s: softreset failed (waited %d usec)\n", - __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); + pr_warn("%s: %s: softreset failed (waited %d usec)\n", + __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); else pr_debug("%s: %s: softreset in %d usec\n", __func__, oh->name, c); diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index b456b4471f35..b9d8e47ffe8e 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -99,7 +99,7 @@ int omap_i2c_reset(struct omap_hwmod *oh) MAX_MODULE_SOFTRESET_WAIT, c); if (c == MAX_MODULE_SOFTRESET_WAIT) - pr_warning("%s: %s: softreset failed (waited %d usec)\n", + pr_warn("%s: %s: softreset failed (waited %d usec)\n", __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); else pr_debug("%s: %s: softreset in %d usec\n", __func__, diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index d42022f2a71e..53841dea80ea 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void) default: /* Unknown default to latest silicon rev as default*/ - pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n", + pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n", __func__, idcode, hawkeye, rev); omap_revision = DRA752_REV_ES1_1; } diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8f559450c876..03cbb16898a3 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -53,6 +53,7 @@ #include "prm2xxx.h" #include "prm3xxx.h" #include "prm44xx.h" +#include "opp2xxx.h" /* * omap_clk_soc_init: points to a function that does the SoC-specific @@ -230,15 +231,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .length = L4_PER_44XX_SIZE, .type = MT_DEVICE, }, -#ifdef CONFIG_OMAP4_ERRATA_I688 - { - .virtual = OMAP4_SRAM_VA, - .pfn = __phys_to_pfn(OMAP4_SRAM_PA), - .length = PAGE_SIZE, - .type = MT_MEMORY_RW_SO, - }, -#endif - }; #endif @@ -268,14 +260,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .length = L4_PER_54XX_SIZE, .type = MT_DEVICE, }, -#ifdef CONFIG_OMAP4_ERRATA_I688 - { - .virtual = OMAP4_SRAM_VA, - .pfn = __phys_to_pfn(OMAP4_SRAM_PA), - .length = PAGE_SIZE, - .type = MT_MEMORY_RW_SO, - }, -#endif }; #endif @@ -410,7 +394,8 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap2420_clk_init; + omap_clk_soc_init = omap2420_dt_clk_init; + rate_table = omap2420_rate_table; } void __init omap2420_init_late(void) @@ -439,7 +424,8 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap2430_clk_init; + omap_clk_soc_init = omap2430_dt_clk_init; + rate_table = omap2430_rate_table; } void __init omap2430_init_late(void) @@ -664,6 +650,7 @@ void __init omap5_init_early(void) omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap4_pm_init_early(); omap_prm_base_init(); omap_cm_base_init(); omap44xx_prm_init(); @@ -679,6 +666,8 @@ void __init omap5_init_early(void) void __init omap5_init_late(void) { omap_common_late_init(); + omap4_pm_init(); + omap2_clk_enable_autoidle_all(); } #endif @@ -692,6 +681,7 @@ void __init dra7xx_init_early(void) omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap4_pm_init_early(); omap_prm_base_init(); omap_cm_base_init(); omap44xx_prm_init(); @@ -706,6 +696,8 @@ void __init dra7xx_init_early(void) void __init dra7xx_init_late(void) { omap_common_late_init(); + omap4_pm_init(); + omap2_clk_enable_autoidle_all(); } #endif @@ -728,9 +720,19 @@ int __init omap_clk_init(void) if (!omap_clk_soc_init) return 0; + ti_clk_init_features(); + ret = of_prcm_init(); - if (!ret) - ret = omap_clk_soc_init(); + if (ret) + return ret; + + of_clk_init(NULL); + + ti_dt_clk_init_retry_clks(); + + ti_dt_clockdomains_setup(); + + ret = omap_clk_soc_init(); return ret; } diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c deleted file mode 100644 index 35b8590c322e..000000000000 --- a/arch/arm/mach-omap2/irq.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/irq.c - * - * Interrupt handler for OMAP2 boards. - * - * Copyright (C) 2005 Nokia Corporation - * Author: Paul Mundt <paul.mundt@nokia.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/io.h> - -#include <asm/exception.h> -#include <asm/mach/irq.h> -#include <linux/irqdomain.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#include "soc.h" -#include "iomap.h" -#include "common.h" - -/* selected INTC register offsets */ - -#define INTC_REVISION 0x0000 -#define INTC_SYSCONFIG 0x0010 -#define INTC_SYSSTATUS 0x0014 -#define INTC_SIR 0x0040 -#define INTC_CONTROL 0x0048 -#define INTC_PROTECTION 0x004C -#define INTC_IDLE 0x0050 -#define INTC_THRESHOLD 0x0068 -#define INTC_MIR0 0x0084 -#define INTC_MIR_CLEAR0 0x0088 -#define INTC_MIR_SET0 0x008c -#define INTC_PENDING_IRQ0 0x0098 -/* Number of IRQ state bits in each MIR register */ -#define IRQ_BITS_PER_REG 32 - -#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) -#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) -#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ -#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ -#define INTCPS_NR_MIR_REGS 3 -#define INTCPS_NR_IRQS 96 - -/* - * OMAP2 has a number of different interrupt controllers, each interrupt - * controller is identified as its own "bank". Register definitions are - * fairly consistent for each bank, but not all registers are implemented - * for each bank.. when in doubt, consult the TRM. - */ -static struct omap_irq_bank { - void __iomem *base_reg; - unsigned int nr_irqs; -} __attribute__ ((aligned(4))) irq_banks[] = { - { - /* MPU INTC */ - .nr_irqs = 96, - }, -}; - -static struct irq_domain *domain; - -/* Structure to save interrupt controller context */ -struct omap3_intc_regs { - u32 sysconfig; - u32 protection; - u32 idle; - u32 threshold; - u32 ilr[INTCPS_NR_IRQS]; - u32 mir[INTCPS_NR_MIR_REGS]; -}; - -/* INTC bank register get/set */ - -static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) -{ - writel_relaxed(val, bank->base_reg + reg); -} - -static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) -{ - return readl_relaxed(bank->base_reg + reg); -} - -/* XXX: FIQ and additional INTC support (only MPU at the moment) */ -static void omap_ack_irq(struct irq_data *d) -{ - intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); -} - -static void omap_mask_ack_irq(struct irq_data *d) -{ - irq_gc_mask_disable_reg(d); - omap_ack_irq(d); -} - -static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) -{ - unsigned long tmp; - - tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; - pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", - bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); - - tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); - tmp |= 1 << 1; /* soft reset */ - intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG); - - while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1)) - /* Wait for reset to complete */; - - /* Enable autoidle */ - intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG); -} - -int omap_irq_pending(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { - struct omap_irq_bank *bank = irq_banks + i; - int irq; - - for (irq = 0; irq < bank->nr_irqs; irq += 32) - if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 + - ((irq >> 5) << 5))) - return 1; - } - return 0; -} - -static __init void -omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, - handle_level_irq); - ct = gc->chip_types; - ct->chip.irq_ack = omap_mask_ack_irq; - ct->chip.irq_mask = irq_gc_mask_disable_reg; - ct->chip.irq_unmask = irq_gc_unmask_enable_reg; - ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; - - ct->regs.enable = INTC_MIR_CLEAR0; - ct->regs.disable = INTC_MIR_SET0; - irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, - IRQ_NOREQUEST | IRQ_NOPROBE, 0); -} - -static void __init omap_init_irq(u32 base, int nr_irqs, - struct device_node *node) -{ - void __iomem *omap_irq_base; - unsigned long nr_of_irqs = 0; - unsigned int nr_banks = 0; - int i, j, irq_base; - - omap_irq_base = ioremap(base, SZ_4K); - if (WARN_ON(!omap_irq_base)) - return; - - irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); - if (irq_base < 0) { - pr_warn("Couldn't allocate IRQ numbers\n"); - irq_base = 0; - } - - domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0, - &irq_domain_simple_ops, NULL); - - for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { - struct omap_irq_bank *bank = irq_banks + i; - - bank->nr_irqs = nr_irqs; - - /* Static mapping, never released */ - bank->base_reg = ioremap(base, SZ_4K); - if (!bank->base_reg) { - pr_err("Could not ioremap irq bank%i\n", i); - continue; - } - - omap_irq_bank_init_one(bank); - - for (j = 0; j < bank->nr_irqs; j += 32) - omap_alloc_gc(bank->base_reg + j, j + irq_base, 32); - - nr_of_irqs += bank->nr_irqs; - nr_banks++; - } - - pr_info("Total of %ld interrupts on %d active controller%s\n", - nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); -} - -void __init omap2_init_irq(void) -{ - omap_init_irq(OMAP24XX_IC_BASE, 96, NULL); -} - -void __init omap3_init_irq(void) -{ - omap_init_irq(OMAP34XX_IC_BASE, 96, NULL); -} - -void __init ti81xx_init_irq(void) -{ - omap_init_irq(OMAP34XX_IC_BASE, 128, NULL); -} - -static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs) -{ - u32 irqnr; - int handled_irq = 0; - - do { - irqnr = readl_relaxed(base_addr + 0x98); - if (irqnr) - goto out; - - irqnr = readl_relaxed(base_addr + 0xb8); - if (irqnr) - goto out; - - irqnr = readl_relaxed(base_addr + 0xd8); -#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX) - if (irqnr) - goto out; - irqnr = readl_relaxed(base_addr + 0xf8); -#endif - -out: - if (!irqnr) - break; - - irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET); - irqnr &= ACTIVEIRQ_MASK; - - if (irqnr) { - irqnr = irq_find_mapping(domain, irqnr); - handle_IRQ(irqnr, regs); - handled_irq = 1; - } - } while (irqnr); - - /* If an irq is masked or deasserted while active, we will - * keep ending up here with no irq handled. So remove it from - * the INTC with an ack.*/ - if (!handled_irq) - omap_ack_irq(NULL); -} - -asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs) -{ - void __iomem *base_addr = OMAP2_IRQ_BASE; - omap_intc_handle_irq(base_addr, regs); -} - -int __init intc_of_init(struct device_node *node, - struct device_node *parent) -{ - struct resource res; - u32 nr_irq = 96; - - if (WARN_ON(!node)) - return -ENODEV; - - if (of_address_to_resource(node, 0, &res)) { - WARN(1, "unable to get intc registers\n"); - return -EINVAL; - } - - if (of_property_read_u32(node, "ti,intc-size", &nr_irq)) - pr_warn("unable to get intc-size, default to %d\n", nr_irq); - - omap_init_irq(res.start, nr_irq, of_node_get(node)); - - return 0; -} - -static struct of_device_id irq_match[] __initdata = { - { .compatible = "ti,omap2-intc", .data = intc_of_init, }, - { } -}; - -void __init omap_intc_of_init(void) -{ - of_irq_init(irq_match); -} - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) -static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; - -void omap_intc_save_context(void) -{ - int ind = 0, i = 0; - for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { - struct omap_irq_bank *bank = irq_banks + ind; - intc_context[ind].sysconfig = - intc_bank_read_reg(bank, INTC_SYSCONFIG); - intc_context[ind].protection = - intc_bank_read_reg(bank, INTC_PROTECTION); - intc_context[ind].idle = - intc_bank_read_reg(bank, INTC_IDLE); - intc_context[ind].threshold = - intc_bank_read_reg(bank, INTC_THRESHOLD); - for (i = 0; i < INTCPS_NR_IRQS; i++) - intc_context[ind].ilr[i] = - intc_bank_read_reg(bank, (0x100 + 0x4*i)); - for (i = 0; i < INTCPS_NR_MIR_REGS; i++) - intc_context[ind].mir[i] = - intc_bank_read_reg(&irq_banks[0], INTC_MIR0 + - (0x20 * i)); - } -} - -void omap_intc_restore_context(void) -{ - int ind = 0, i = 0; - - for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { - struct omap_irq_bank *bank = irq_banks + ind; - intc_bank_write_reg(intc_context[ind].sysconfig, - bank, INTC_SYSCONFIG); - intc_bank_write_reg(intc_context[ind].sysconfig, - bank, INTC_SYSCONFIG); - intc_bank_write_reg(intc_context[ind].protection, - bank, INTC_PROTECTION); - intc_bank_write_reg(intc_context[ind].idle, - bank, INTC_IDLE); - intc_bank_write_reg(intc_context[ind].threshold, - bank, INTC_THRESHOLD); - for (i = 0; i < INTCPS_NR_IRQS; i++) - intc_bank_write_reg(intc_context[ind].ilr[i], - bank, (0x100 + 0x4*i)); - for (i = 0; i < INTCPS_NR_MIR_REGS; i++) - intc_bank_write_reg(intc_context[ind].mir[i], - &irq_banks[0], INTC_MIR0 + (0x20 * i)); - } - /* MIRs are saved and restore with other PRCM registers */ -} - -void omap3_intc_suspend(void) -{ - /* A pending interrupt would prevent OMAP from entering suspend */ - omap_ack_irq(NULL); -} - -void omap3_intc_prepare_idle(void) -{ - /* - * Disable autoidle as it can stall interrupt controller, - * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) - */ - intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); -} - -void omap3_intc_resume_idle(void) -{ - /* Re-enable autoidle */ - intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG); -} - -asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) -{ - void __iomem *base_addr = OMAP3_IRQ_BASE; - omap_intc_handle_irq(base_addr, regs); -} -#endif /* CONFIG_ARCH_OMAP3 */ diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index 828e0db3d943..8bdf182422bd 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c @@ -76,8 +76,8 @@ int omap_msdi_reset(struct omap_hwmod *oh) MAX_MODULE_SOFTRESET_WAIT, c); if (c == MAX_MODULE_SOFTRESET_WAIT) - pr_warning("%s: %s: softreset failed (waited %d usec)\n", - __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); + pr_warn("%s: %s: softreset failed (waited %d usec)\n", + __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); else pr_debug("%s: %s: softreset in %d usec\n", __func__, oh->name, c); diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index f62f7537d899..78064b0d4db5 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -681,29 +681,19 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) { - char buf[OMAP_MUX_MAX_ARG_CHAR]; struct seq_file *seqf; struct omap_mux *m; - unsigned long val; - int buf_size, ret; + u16 val; + int ret; struct omap_mux_partition *partition; if (count > OMAP_MUX_MAX_ARG_CHAR) return -EINVAL; - memset(buf, 0, sizeof(buf)); - buf_size = min(count, sizeof(buf) - 1); - - if (copy_from_user(buf, user_buf, buf_size)) - return -EFAULT; - - ret = strict_strtoul(buf, 0x10, &val); + ret = kstrtou16_from_user(user_buf, count, 0x10, &val); if (ret < 0) return ret; - if (val > 0xffff) - return -EINVAL; - seqf = file->private_data; m = seqf->private; @@ -711,7 +701,7 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file, if (!partition) return -ENODEV; - omap_mux_write(partition, (u16)val, m->reg_offset); + omap_mux_write(partition, val, m->reg_offset); *ppos += count; return count; @@ -824,7 +814,7 @@ int __init omap_mux_late_init(void) "hwmod_io", omap_mux_late_init); if (ret) - pr_warning("mux: Failed to setup hwmod io irq %d\n", ret); + pr_warn("mux: Failed to setup hwmod io irq %d\n", ret); return 0; } @@ -917,14 +907,14 @@ static void __init omap_mux_set_cmdline_signals(void) while ((token = strsep(&next_opt, ",")) != NULL) { char *keyval, *name; - unsigned long val; + u16 val; keyval = token; name = strsep(&keyval, "="); if (name) { int res; - res = strict_strtoul(keyval, 0x10, &val); + res = kstrtou16(keyval, 0x10, &val); if (res < 0) continue; diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 4001325f90fb..6944ae3674e8 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -56,6 +56,7 @@ #include "omap4-sar-layout.h" #include "pm.h" #include "prcm_mpu44xx.h" +#include "prcm_mpu54xx.h" #include "prminst44xx.h" #include "prcm44xx.h" #include "prm44xx.h" @@ -68,7 +69,6 @@ struct omap4_cpu_pm_info { void __iomem *scu_sar_addr; void __iomem *wkup_sar_addr; void __iomem *l2x0_sar_addr; - void (*secondary_startup)(void); }; /** @@ -76,6 +76,7 @@ struct omap4_cpu_pm_info { * @finish_suspend: CPU suspend finisher function pointer * @resume: CPU resume function pointer * @scu_prepare: CPU Snoop Control program function pointer + * @hotplug_restart: CPU restart function pointer * * Structure holds functions pointer for CPU low power operations like * suspend, resume and scu programming. @@ -84,11 +85,13 @@ struct cpu_pm_ops { int (*finish_suspend)(unsigned long cpu_state); void (*resume)(void); void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state); + void (*hotplug_restart)(void); }; static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); static struct powerdomain *mpuss_pd; static void __iomem *sar_base; +static u32 cpu_context_offset; static int default_finish_suspend(unsigned long cpu_state) { @@ -106,6 +109,7 @@ struct cpu_pm_ops omap_pm_ops = { .finish_suspend = default_finish_suspend, .resume = dummy_cpu_resume, .scu_prepare = dummy_scu_prepare, + .hotplug_restart = dummy_cpu_resume, }; /* @@ -116,7 +120,8 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) { struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); - writel_relaxed(addr, pm_info->wkup_sar_addr); + if (pm_info->wkup_sar_addr) + writel_relaxed(addr, pm_info->wkup_sar_addr); } /* @@ -141,7 +146,8 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) break; } - writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); + if (pm_info->scu_sar_addr) + writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); } /* Helper functions for MPUSS OSWR */ @@ -161,14 +167,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) if (cpu_id) { reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, - OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); + cpu_context_offset); omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, - OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); + cpu_context_offset); } else { reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, - OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); + cpu_context_offset); omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, - OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); + cpu_context_offset); } } @@ -179,7 +185,8 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) { struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); - writel_relaxed(save_state, pm_info->l2x0_sar_addr); + if (pm_info->l2x0_sar_addr) + writel_relaxed(save_state, pm_info->l2x0_sar_addr); } /* @@ -189,10 +196,14 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) #ifdef CONFIG_CACHE_L2X0 static void __init save_l2x0_context(void) { - writel_relaxed(l2x0_saved_regs.aux_ctrl, - sar_base + L2X0_AUXCTRL_OFFSET); - writel_relaxed(l2x0_saved_regs.prefetch_ctrl, - sar_base + L2X0_PREFETCH_CTRL_OFFSET); + void __iomem *l2x0_base = omap4_get_l2cache_base(); + + if (l2x0_base && sar_base) { + writel_relaxed(l2x0_saved_regs.aux_ctrl, + sar_base + L2X0_AUXCTRL_OFFSET); + writel_relaxed(l2x0_saved_regs.prefetch_ctrl, + sar_base + L2X0_PREFETCH_CTRL_OFFSET); + } } #else static void __init save_l2x0_context(void) @@ -231,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) save_state = 1; break; case PWRDM_POWER_RET: + if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) { + save_state = 0; + break; + } default: /* * CPUx CSWR is invalid hardware state. Also CPUx OSWR @@ -298,12 +313,16 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) if (omap_rev() == OMAP4430_REV_ES1_0) return -ENXIO; + /* Use the achievable power state for the domain */ + power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm, + false, power_state); + if (power_state == PWRDM_POWER_OFF) cpu_state = 1; pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); - set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); + set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart)); omap_pm_ops.scu_prepare(cpu, power_state); /* @@ -319,6 +338,21 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) /* + * Enable Mercury Fast HG retention mode by default. + */ +static void enable_mercury_retention_mode(void) +{ + u32 reg; + + reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST, + OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET); + /* Enable HG_EN, HG_RAMPUP = fast mode */ + reg |= BIT(24) | BIT(25); + omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST, + OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET); +} + +/* * Initialise OMAP4 MPUSS */ int __init omap4_mpuss_init(void) @@ -330,13 +364,17 @@ int __init omap4_mpuss_init(void) return -ENODEV; } - sar_base = omap4_get_sar_ram_base(); + if (cpu_is_omap44xx()) + sar_base = omap4_get_sar_ram_base(); /* Initilaise per CPU PM information */ pm_info = &per_cpu(omap4_pm_info, 0x0); - pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; - pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; - pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; + if (sar_base) { + pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; + pm_info->wkup_sar_addr = sar_base + + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; + pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; + } pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); if (!pm_info->pwrdm) { pr_err("Lookup failed for CPU0 pwrdm\n"); @@ -351,13 +389,12 @@ int __init omap4_mpuss_init(void) pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); pm_info = &per_cpu(omap4_pm_info, 0x1); - pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; - pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; - pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; - if (cpu_is_omap446x()) - pm_info->secondary_startup = omap4460_secondary_startup; - else - pm_info->secondary_startup = omap4_secondary_startup; + if (sar_base) { + pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; + pm_info->wkup_sar_addr = sar_base + + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; + pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; + } pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); if (!pm_info->pwrdm) { @@ -380,20 +417,27 @@ int __init omap4_mpuss_init(void) pwrdm_clear_all_prev_pwrst(mpuss_pd); mpuss_clear_prev_logic_pwrst(); - /* Save device type on scratchpad for low level code to use */ - if (omap_type() != OMAP2_DEVICE_TYPE_GP) - writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET); - else - writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET); - - save_l2x0_context(); + if (sar_base) { + /* Save device type on scratchpad for low level code to use */ + writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0, + sar_base + OMAP_TYPE_OFFSET); + save_l2x0_context(); + } if (cpu_is_omap44xx()) { omap_pm_ops.finish_suspend = omap4_finish_suspend; omap_pm_ops.resume = omap4_cpu_resume; omap_pm_ops.scu_prepare = scu_pwrst_prepare; + omap_pm_ops.hotplug_restart = omap4_secondary_startup; + cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET; + } else if (soc_is_omap54xx() || soc_is_dra7xx()) { + cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET; + enable_mercury_retention_mode(); } + if (cpu_is_omap446x()) + omap_pm_ops.hotplug_restart = omap4460_secondary_startup; + return 0; } diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 3e97c6c8ecf1..dec2b05d184b 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -45,6 +45,7 @@ #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 +#define OMAP5_MON_AMBA_IF_INDEX 0x108 /* Secure PPA(Primary Protected Application) APIs */ #define OMAP4_PPA_L2_POR_INDEX 0x23 diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 37843a7d3639..f961c46453b9 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -32,6 +32,7 @@ #include "soc.h" #include "omap4-sar-layout.h" #include "common.h" +#include "pm.h" #define AM43XX_NR_REG_BANKS 7 #define AM43XX_IRQS 224 @@ -381,7 +382,7 @@ static struct notifier_block irq_notifier_block = { static void __init irq_pm_init(void) { /* FIXME: Remove this when MPU OSWR support is added */ - if (!soc_is_omap54xx()) + if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) cpu_pm_register_notifier(&irq_notifier_block); } #else @@ -406,6 +407,7 @@ int __init omap_wakeupgen_init(void) { int i; unsigned int boot_cpu = smp_processor_id(); + u32 val; /* Not supported on OMAP4 ES1.0 silicon */ if (omap_rev() == OMAP4430_REV_ES1_0) { @@ -451,6 +453,22 @@ int __init omap_wakeupgen_init(void) for (i = 0; i < max_irqs; i++) irq_target_cpu[i] = boot_cpu; + /* + * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE + * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together. + * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode + * independently. + * This needs to be set one time thanks to always ON domain. + * + * We do not support ES1 behavior anymore. OMAP5 is assumed to be + * ES2.0, and the same is applicable for DRA7. + */ + if (soc_is_omap54xx() || soc_is_dra7xx()) { + val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE); + val |= BIT(5); + omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val); + } + irq_hotplug_init(); irq_pm_init(); diff --git a/arch/arm/mach-omap2/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h index b0fd16f5c391..b3c8eccfae79 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.h +++ b/arch/arm/mach-omap2/omap-wakeupgen.h @@ -27,6 +27,7 @@ #define OMAP_WKG_ENB_E_1 0x420 #define OMAP_AUX_CORE_BOOT_0 0x800 #define OMAP_AUX_CORE_BOOT_1 0x804 +#define OMAP_AMBA_IF_MODE 0x80c #define OMAP_PTMSYNCREQ_MASK 0xc00 #define OMAP_PTMSYNCREQ_EN 0xc04 #define OMAP_TIMESTAMPCYCLELO 0xc08 diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index a0fe747634c1..16b20cedc38d 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -25,6 +25,7 @@ #include <linux/irqchip/irq-crossbar.h> #include <linux/of_address.h> #include <linux/reboot.h> +#include <linux/genalloc.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/map.h> @@ -71,6 +72,26 @@ void omap_bus_sync(void) } EXPORT_SYMBOL(omap_bus_sync); +static int __init omap4_sram_init(void) +{ + struct device_node *np; + struct gen_pool *sram_pool; + + np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); + if (!np) + pr_warn("%s:Unable to allocate sram needed to handle errata I688\n", + __func__); + sram_pool = of_get_named_gen_pool(np, "sram", 0); + if (!sram_pool) + pr_warn("%s:Unable to get sram pool needed to handle errata I688\n", + __func__); + else + sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE); + + return 0; +} +omap_arch_initcall(omap4_sram_init); + /* Steal one page physical memory for barrier implementation */ int __init omap_barrier_reserve_memblock(void) { @@ -91,7 +112,6 @@ void __init omap_barriers_init(void) dram_io_desc[0].type = MT_MEMORY_RW_SO; iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); dram_sync = (void __iomem *) dram_io_desc[0].virtual; - sram_sync = (void __iomem *) OMAP4_SRAM_VA; pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", (long long) paddr, dram_io_desc[0].virtual); diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 01ef59def44b..8c58b71c2727 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias, r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); if (!IS_ERR(r)) { - dev_warn(&od->pdev->dev, + dev_dbg(&od->pdev->dev, "alias %s already exists\n", clk_alias); clk_put(r); return; @@ -917,6 +917,10 @@ static int __init omap_device_late_idle(struct device *dev, void *data) static int __init omap_device_late_init(void) { bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle); + + WARN(!of_have_populated_dt(), + "legacy booting deprecated, please update to boot with .dts\n"); + return 0; } omap_late_initcall_sync(omap_device_late_init); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 6c074f37cdd2..716247ed9e0c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -769,8 +769,8 @@ static int _init_main_clk(struct omap_hwmod *oh) oh->_clk = clk_get(NULL, oh->main_clk); if (IS_ERR(oh->_clk)) { - pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", - oh->name, oh->main_clk); + pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", + oh->name, oh->main_clk); return -EINVAL; } /* @@ -814,8 +814,8 @@ static int _init_interface_clks(struct omap_hwmod *oh) c = clk_get(NULL, os->clk); if (IS_ERR(c)) { - pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", - oh->name, os->clk); + pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n", + oh->name, os->clk); ret = -EINVAL; continue; } @@ -851,8 +851,8 @@ static int _init_opt_clks(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { c = clk_get(NULL, oc->clk); if (IS_ERR(c)) { - pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", - oh->name, oc->clk); + pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n", + oh->name, oc->clk); ret = -EINVAL; continue; } @@ -1576,7 +1576,7 @@ static int _init_clkdm(struct omap_hwmod *oh) oh->clkdm = clkdm_lookup(oh->clkdm_name); if (!oh->clkdm) { - pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", + pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n", oh->name, oh->clkdm_name); return 0; } @@ -1616,7 +1616,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) if (!ret) oh->_state = _HWMOD_STATE_CLKS_INITED; else - pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); + pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name); return ret; } @@ -1739,7 +1739,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) _disable_clocks(oh); if (ret == -EBUSY) - pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); + pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); if (!ret) { /* @@ -1953,8 +1953,8 @@ static int _ocp_softreset(struct omap_hwmod *oh) c = _wait_softreset_complete(oh); if (c == MAX_MODULE_SOFTRESET_WAIT) { - pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", - oh->name, MAX_MODULE_SOFTRESET_WAIT); + pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n", + oh->name, MAX_MODULE_SOFTRESET_WAIT); ret = -ETIMEDOUT; goto dis_opt_clks; } else { @@ -2065,7 +2065,7 @@ static void _reconfigure_io_chain(void) spin_lock_irqsave(&io_chain_lock, flags); - if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl()) + if (cpu_is_omap34xx()) omap3xxx_prm_reconfigure_io_chain(); else if (cpu_is_omap44xx()) omap44xx_prm_reconfigure_io_chain(); @@ -2185,6 +2185,8 @@ static int _enable(struct omap_hwmod *oh) oh->mux->pads_dynamic))) { omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); _reconfigure_io_chain(); + } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) { + _reconfigure_io_chain(); } _add_initiator_dep(oh, mpu_oh); @@ -2291,6 +2293,8 @@ static int _idle(struct omap_hwmod *oh) if (oh->mux && oh->mux->pads_dynamic) { omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); _reconfigure_io_chain(); + } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) { + _reconfigure_io_chain(); } oh->_state = _HWMOD_STATE_IDLE; @@ -2614,8 +2618,8 @@ static int __init _setup_reset(struct omap_hwmod *oh) if (oh->rst_lines_cnt == 0) { r = _enable(oh); if (r) { - pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", - oh->name, oh->_state); + pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n", + oh->name, oh->_state); return -EINVAL; } } @@ -3345,6 +3349,9 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) if (!ois) return 0; + if (ois[0] == NULL) /* Empty list */ + return 0; + if (!linkspace) { if (_alloc_linkspace(ois)) { pr_err("omap_hwmod: could not allocate link space\n"); diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0f97d635ff90..512f809a3f4d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -514,6 +514,9 @@ struct omap_hwmod_omap4_prcm { * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module * out of idle, but rely on smart-idle to the put it back in idle, * so the wakeups are still functional (Only known case for now is UART) + * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up + * events by calling _reconfigure_io_chain() when a device is enabled + * or idled. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -528,6 +531,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_BLOCK_WFI (1 << 10) #define HWMOD_FORCE_MSTANDBY (1 << 11) #define HWMOD_SWSUP_SIDLE_ACT (1 << 12) +#define HWMOD_RECONFIG_IO_CHAIN (1 << 13) /* * omap_hwmod._int_flags definitions diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 2f15979c2e9c..65b1647092bd 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -16,7 +16,6 @@ #include <linux/i2c-omap.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/omap-dma.h> -#include <linux/platform_data/mailbox-omap.h> #include <plat/dmtimer.h> #include "omap_hwmod.h" @@ -163,18 +162,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { }; /* mailbox */ -static struct omap_mbox_dev_info omap2420_mailbox_info[] = { - { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 }, - { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 }, -}; - -static struct omap_mbox_pdata omap2420_mailbox_attrs = { - .num_users = 4, - .num_fifos = 6, - .info_cnt = ARRAY_SIZE(omap2420_mailbox_info), - .info = omap2420_mailbox_info, -}; - static struct omap_hwmod omap2420_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -188,7 +175,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &omap2420_mailbox_attrs, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 6d1b60902179..c2555cb95e71 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -17,7 +17,6 @@ #include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/omap-dma.h> -#include <linux/platform_data/mailbox-omap.h> #include <plat/dmtimer.h> #include "omap_hwmod.h" @@ -161,17 +160,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { }; /* mailbox */ -static struct omap_mbox_dev_info omap2430_mailbox_info[] = { - { .name = "dsp", .tx_id = 0, .rx_id = 1 }, -}; - -static struct omap_mbox_pdata omap2430_mailbox_attrs = { - .num_users = 4, - .num_fifos = 6, - .info_cnt = ARRAY_SIZE(omap2430_mailbox_info), - .info = omap2430_mailbox_info, -}; - static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -185,7 +173,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &omap2430_mailbox_attrs, }; /* mcspi3 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c index 0413daba2dba..c1e98d589100 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c @@ -152,15 +152,6 @@ struct omap_hwmod_addr_space omap2_dma_system_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2_mailbox_addrs[] = { - { - .pa_start = 0x48094000, - .pa_end = 0x48094000 + SZ_512 - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = { { .name = "mpu", diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 5da7a42a6d90..c6c6384de867 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -37,46 +37,6 @@ struct omap_hwmod_class omap2_uart_class = { }; /* - * 'dss' class - * display sub-system - */ - -static struct omap_hwmod_class_sysconfig omap2_dss_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class omap2_dss_hwmod_class = { - .name = "dss", - .sysc = &omap2_dss_sysc, - .reset = omap_dss_reset, -}; - -/* - * 'rfbi' class - * remote frame buffer interface - */ - -static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class omap2_rfbi_hwmod_class = { - .name = "rfbi", - .sysc = &omap2_rfbi_sysc, -}; - -/* * 'venc' class * video encoder */ diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index e2db378b849e..8f5989d48a80 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -317,21 +317,11 @@ struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { - { - .pa_start = 0x480C8000, - .pa_end = 0x480C8000 + (SZ_4K - 1), - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4 ls -> mailbox */ struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mailbox_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mailbox_addrs, .user = OCP_USER_MPU, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e9516b454e76..2a78b093c0ce 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -490,7 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { .mpu_irqs = omap2_uart1_mpu_irqs, .sdma_reqs = omap2_uart1_sdma_reqs, .main_clk = "uart1_fck", - .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -509,7 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { .mpu_irqs = omap2_uart2_mpu_irqs, .sdma_reqs = omap2_uart2_sdma_reqs, .main_clk = "uart2_fck", - .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, .prcm = { .omap2 = { .module_offs = CORE_MOD, @@ -529,7 +529,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { .sdma_reqs = omap2_uart3_sdma_reqs, .main_clk = "uart3_fck", .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | - HWMOD_SWSUP_SIDLE_ACT, + HWMOD_SWSUP_SIDLE, .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, @@ -559,7 +559,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { .mpu_irqs = uart4_mpu_irqs, .sdma_reqs = uart4_sdma_reqs, .main_clk = "uart4_fck", - .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, @@ -1730,8 +1730,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY * signal when MIDLEMODE is set to force-idle. */ - .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE - | HWMOD_FORCE_MSTANDBY, + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | + HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN, }; /* usb_otg_hs */ diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 5c2cc8083fdd..fea01aa3ef42 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -19,6 +19,8 @@ #include "omap_hwmod.h" #include "omap_hwmod_33xx_43xx_common_data.h" #include "prcm43xx.h" +#include "omap_hwmod_common_data.h" + /* IP blocks */ static struct omap_hwmod am43xx_l4_hs_hwmod = { @@ -415,6 +417,72 @@ static struct omap_hwmod am43xx_qspi_hwmod = { }, }; +/* dss */ + +static struct omap_hwmod am43xx_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "disp_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* dispc */ + +struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = { + .manager_count = 1, + .has_framedonetv_irq = 0 +}; + +static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am43xx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &am43xx_dispc_sysc, +}; + +static struct omap_hwmod am43xx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &am43xx_dispc_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "disp_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, + }, + }, + .dev_attr = &am43xx_dss_dispc_dev_attr, +}; + +/* rfbi */ + +static struct omap_hwmod am43xx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "disp_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, + }, + }, +}; + /* Interfaces */ static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { .master = &am33xx_l3_main_hwmod, @@ -654,6 +722,34 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if am43xx_dss__l3_main = { + .master = &am43xx_dss_core_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am43xx_dss_core_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am43xx_dss_dispc_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am43xx_dss_rfbi_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_wkup__synctimer, &am43xx_l4_ls__timer8, @@ -748,6 +844,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l4_ls__ocp2scp1, &am43xx_l3_s__usbotgss0, &am43xx_l3_s__usbotgss1, + &am43xx_dss__l3_main, + &am43xx_l4_ls__dss, + &am43xx_l4_ls__dss_dispc, + &am43xx_l4_ls__dss_rfbi, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index b4acc0a7576f..44e5634bba34 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -4138,21 +4138,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { - { - .pa_start = 0x4a0f4000, - .pa_end = 0x4a0f41ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> mailbox */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_mailbox_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 284324f2b98a..5684f112654b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -35,6 +35,7 @@ #include "i2c.h" #include "mmc.h" #include "wd_timer.h" +#include "soc.h" /* Base offset for all DRA7XX interrupts external to MPUSS */ #define DRA7XX_IRQ_GIC_START 32 @@ -273,6 +274,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { }; /* + * 'gmac' class + * cpsw/gmac sub system + */ +static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x8, + .syss_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | + MSTANDBY_NO), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class dra7xx_gmac_hwmod_class = { + .name = "gmac", + .sysc = &dra7xx_gmac_sysc, +}; + +static struct omap_hwmod dra7xx_gmac_hwmod = { + .name = "gmac", + .class = &dra7xx_gmac_hwmod_class, + .clkdm_name = "gmac_clkdm", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "dpll_gmac_ck", + .mpu_rt_idx = 1, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mdio' class + */ +static struct omap_hwmod_class dra7xx_mdio_hwmod_class = { + .name = "davinci_mdio", +}; + +static struct omap_hwmod dra7xx_mdio_hwmod = { + .name = "davinci_mdio", + .class = &dra7xx_mdio_hwmod_class, + .clkdm_name = "gmac_clkdm", + .main_clk = "dpll_gmac_ck", +}; + +/* * 'dcan' class * */ @@ -343,19 +394,10 @@ static struct omap_dma_dev_attr dma_dev_attr = { }; /* dma_system */ -static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = { - { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START }, - { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START }, - { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START }, - { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod dra7xx_dma_system_hwmod = { .name = "dma_system", .class = &dra7xx_dma_hwmod_class, .clkdm_name = "dma_clkdm", - .mpu_irqs = dra7xx_dma_system_irqs, .main_clk = "l3_iclk_div", .prcm = { .omap4 = { @@ -939,6 +981,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { }; /* + * 'mailbox' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &dra7xx_mailbox_sysc, +}; + +/* mailbox1 */ +static struct omap_hwmod dra7xx_mailbox1_hwmod = { + .name = "mailbox1", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox2 */ +static struct omap_hwmod dra7xx_mailbox2_hwmod = { + .name = "mailbox2", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox3 */ +static struct omap_hwmod dra7xx_mailbox3_hwmod = { + .name = "mailbox3", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox4 */ +static struct omap_hwmod dra7xx_mailbox4_hwmod = { + .name = "mailbox4", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox5 */ +static struct omap_hwmod dra7xx_mailbox5_hwmod = { + .name = "mailbox5", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox6 */ +static struct omap_hwmod dra7xx_mailbox6_hwmod = { + .name = "mailbox6", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox7 */ +static struct omap_hwmod dra7xx_mailbox7_hwmod = { + .name = "mailbox7", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox8 */ +static struct omap_hwmod dra7xx_mailbox8_hwmod = { + .name = "mailbox8", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox9 */ +static struct omap_hwmod dra7xx_mailbox9_hwmod = { + .name = "mailbox9", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox10 */ +static struct omap_hwmod dra7xx_mailbox10_hwmod = { + .name = "mailbox10", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox11 */ +static struct omap_hwmod dra7xx_mailbox11_hwmod = { + .name = "mailbox11", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox12 */ +static struct omap_hwmod dra7xx_mailbox12_hwmod = { + .name = "mailbox12", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET, + }, + }, +}; + +/* mailbox13 */ +static struct omap_hwmod dra7xx_mailbox13_hwmod = { + .name = "mailbox13", + .class = &dra7xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'mcspi' class * */ @@ -1215,6 +1445,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { }, }; +/* ocp2scp3 */ +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { + .name = "ocp2scp3", + .class = &dra7xx_ocp2scp_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'PCIE' class + * + */ + +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = { + .name = "pcie", +}; + +/* pcie1 */ +static struct omap_hwmod dra7xx_pcie1_hwmod = { + .name = "pcie1", + .class = &dra7xx_pcie_hwmod_class, + .clkdm_name = "pcie_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* pcie2 */ +static struct omap_hwmod dra7xx_pcie2_hwmod = { + .name = "pcie2", + .class = &dra7xx_pcie_hwmod_class, + .clkdm_name = "pcie_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'PCIE PHY' class + * + */ + +static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = { + .name = "pcie-phy", +}; + +/* pcie1 phy */ +static struct omap_hwmod dra7xx_pcie1_phy_hwmod = { + .name = "pcie1-phy", + .class = &dra7xx_pcie_phy_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* pcie2 phy */ +static struct omap_hwmod dra7xx_pcie2_phy_hwmod = { + .name = "pcie2-phy", + .class = &dra7xx_pcie_phy_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + /* * 'qspi' class * @@ -1249,6 +1570,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = { }; /* + * 'rtcss' class + * + */ +static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { + .sysc_offs = 0x0078, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { + .name = "rtcss", + .sysc = &dra7xx_rtcss_sysc, +}; + +/* rtcss */ +static struct omap_hwmod dra7xx_rtcss_hwmod = { + .name = "rtcss", + .class = &dra7xx_rtcss_hwmod_class, + .clkdm_name = "rtc_clkdm", + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'sata' class * */ @@ -2007,6 +2360,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_gmac_hwmod, + .clk = "dpll_gmac_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = { + .master = &dra7xx_gmac_hwmod, + .slave = &dra7xx_mdio_hwmod, + .user = OCP_USER_MPU, +}; + /* l4_wkup -> dcan1 */ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { .master = &dra7xx_l4_wkup_hwmod, @@ -2254,6 +2620,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> mailbox1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_mailbox1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox5_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox6_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox7_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox8_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox9 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox9_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox10 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox10_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox11 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox11_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox12_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> mailbox13 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_mailbox13_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per1 -> mcspi1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { .master = &dra7xx_l4_per1_hwmod, @@ -2334,6 +2804,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> ocp2scp3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_ocp2scp3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> pcie1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_pcie1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pcie1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> pcie2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_pcie2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pcie2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pcie1 phy */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie1_phy_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pcie2 phy */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pcie2_phy_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { { .pa_start = 0x4b300000, @@ -2352,6 +2878,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per3 -> rtcss */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_rtcss_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { { .name = "sysc", @@ -2650,6 +3184,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_wkup__ctrl_module_wkup, &dra7xx_l4_wkup__dcan1, &dra7xx_l4_per2__dcan2, + &dra7xx_l4_per2__cpgmac0, + &dra7xx_gmac__mdio, &dra7xx_l4_cfg__dma_system, &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, @@ -2670,6 +3206,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__i2c3, &dra7xx_l4_per1__i2c4, &dra7xx_l4_per1__i2c5, + &dra7xx_l4_cfg__mailbox1, + &dra7xx_l4_per3__mailbox2, + &dra7xx_l4_per3__mailbox3, + &dra7xx_l4_per3__mailbox4, + &dra7xx_l4_per3__mailbox5, + &dra7xx_l4_per3__mailbox6, + &dra7xx_l4_per3__mailbox7, + &dra7xx_l4_per3__mailbox8, + &dra7xx_l4_per3__mailbox9, + &dra7xx_l4_per3__mailbox10, + &dra7xx_l4_per3__mailbox11, + &dra7xx_l4_per3__mailbox12, + &dra7xx_l4_per3__mailbox13, &dra7xx_l4_per1__mcspi1, &dra7xx_l4_per1__mcspi2, &dra7xx_l4_per1__mcspi3, @@ -2680,7 +3229,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__mmc4, &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, + &dra7xx_l4_cfg__ocp2scp3, + &dra7xx_l3_main_1__pcie1, + &dra7xx_l4_cfg__pcie1, + &dra7xx_l3_main_1__pcie2, + &dra7xx_l4_cfg__pcie2, + &dra7xx_l4_cfg__pcie1_phy, + &dra7xx_l4_cfg__pcie2_phy, &dra7xx_l3_main_1__qspi, + &dra7xx_l4_per3__rtcss, &dra7xx_l4_cfg__sata, &dra7xx_l4_cfg__smartreflex_core, &dra7xx_l4_cfg__smartreflex_mpu, @@ -2705,7 +3262,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss1, &dra7xx_l4_per3__usb_otg_ss2, &dra7xx_l4_per3__usb_otg_ss3, - &dra7xx_l4_per3__usb_otg_ss4, &dra7xx_l3_main_1__vcp1, &dra7xx_l4_per2__vcp1, &dra7xx_l3_main_1__vcp2, @@ -2714,8 +3270,26 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { NULL, }; +static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { + &dra7xx_l4_per3__usb_otg_ss4, + NULL, +}; + +static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { + NULL, +}; + int __init dra7xx_hwmod_init(void) { + int ret; + omap_hwmod_init(); - return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); + + if (!ret && soc_is_dra74x()) + return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); + else if (!ret && soc_is_dra72x()) + return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + + return ret; } diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 2c38c6b0ee03..11ed5a17dd77 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -33,7 +33,6 @@ extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[]; extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[]; extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[]; extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; -extern struct omap_hwmod_addr_space omap2_mailbox_addrs[]; extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c new file mode 100644 index 000000000000..f21664da25a2 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c @@ -0,0 +1,55 @@ +/* + * omap_hwmod_common_ipblock_data.c - common IP block data for OMAP2+ + * + * Copyright (C) 2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap_hwmod.h" +#include "omap_hwmod_common_data.h" + +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap2_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +struct omap_hwmod_class omap2_dss_hwmod_class = { + .name = "dss", + .sysc = &omap2_dss_sysc, + .reset = omap_dss_reset, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +struct omap_hwmod_class omap2_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap2_rfbi_sysc, +}; + diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 90c88d498485..cec9d6c6442c 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -244,8 +244,8 @@ static void __init nokia_n900_legacy_init(void) /* set IBE to 1 */ rx51_secure_update_aux_cr(BIT(6), 0); } else { - pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n"); - pr_warning("Thumb binaries may crash randomly without this workaround\n"); + pr_warn("RX-51: Not enabling ARM errata 430973 workaround\n"); + pr_warn("Thumb binaries may crash randomly without this workaround\n"); } pr_info("RX-51: Registring OMAP3 HWRNG device\n"); @@ -253,6 +253,11 @@ static void __init nokia_n900_legacy_init(void) } } + +static void __init omap3_tao3530_legacy_init(void) +{ + hsmmc2_internal_input_clk(); +} #endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_ARCH_OMAP4 @@ -336,6 +341,8 @@ static struct pdata_init auxdata_quirks[] __initdata = { struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { #ifdef CONFIG_MACH_NOKIA_N8X0 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), + OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data), + OF_DEV_AUXDATA("tlv320aic3x", 0x18, "2-0018", &n810_aic33_data), #endif #ifdef CONFIG_ARCH_OMAP3 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), @@ -352,6 +359,16 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), #endif +#ifdef CONFIG_SOC_OMAP5 + OF_DEV_AUXDATA("ti,omap5-padconf", 0x4a002840, "4a002840.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,omap5-padconf", 0x4ae0c840, "4ae0c840.pinmux", &pcs_pdata), +#endif +#ifdef CONFIG_SOC_DRA7XX + OF_DEV_AUXDATA("ti,dra7-padconf", 0x4a003400, "4a003400.pinmux", &pcs_pdata), +#endif +#ifdef CONFIG_SOC_AM43XX + OF_DEV_AUXDATA("ti,am437-padconf", 0x44e10800, "44e10800.pinmux", &pcs_pdata), +#endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", &omap4_iommu_pdata), @@ -377,6 +394,7 @@ static struct pdata_init pdata_quirks[] __initdata = { { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, { "ti,am3517-evm", am3517_evm_legacy_init, }, + { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, }, #endif #ifdef CONFIG_ARCH_OMAP4 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, @@ -405,7 +423,7 @@ static void pdata_quirks_check(struct pdata_init *quirks) } } -void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) +void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) { omap_sdrc_init(NULL, NULL); pdata_quirks_check(auxdata_quirks); diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 828aee9ea6a8..58920bc8807b 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -282,7 +282,7 @@ static inline void omap_init_cpufreq(void) if (!of_have_populated_dt()) devinfo.name = "omap-cpufreq"; else - devinfo.name = "cpufreq-cpu0"; + devinfo.name = "cpufreq-dt"; platform_device_register_full(&devinfo); } diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index e150102d6c06..425bfcd67db6 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -101,6 +101,7 @@ static inline void enable_omap3630_toggle_l2_on_restore(void) { } #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ #define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0) +#define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) extern u16 pm44xx_errata; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988ff340..fe01c5a03aa2 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void) /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); + omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); @@ -104,23 +104,18 @@ no_sleep: clk_enable(osc_ck); /* clear CORE wake-up events */ - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ - omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); + omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1); /* MPU domain wake events */ - l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - if (l & 0x01) - omap2_prm_write_mod_reg(0x01, OCP_MOD, - OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - if (l & 0x20) - omap2_prm_write_mod_reg(0x20, OCP_MOD, - OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, + 0x1); - /* Mask future PRCM-to-MPU interrupts */ - omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, + 0x20); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); @@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void) * it is in retention mode. */ if (omap2_allow_mpu_retention()) { /* REVISIT: These write to reserved bits? */ - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); + omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); + omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); /* Try to enter MPU retention */ pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); @@ -249,6 +244,10 @@ static void __init prcm_setup_regs(void) /* Enable wake-up events */ omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, WKUP_MOD, PM_WKEN); + + /* Enable SYS_CLKEN control when all domains idle */ + omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD, + OMAP2_PRCM_CLKSRC_CTRL_OFFSET); } int __init omap2_pm_init(void) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 507d8eeaab95..175564c88a30 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void) } } -/* - * PRCM Interrupt Handler Helper Function - * - * The purpose of this function is to clear any wake-up events latched - * in the PRCM PM_WKST_x registers. It is possible that a wake-up event - * may occur whilst attempting to clear a PM_WKST_x register and thus - * set another bit in this register. A while loop is used to ensure - * that any peripheral wake-up events occurring while attempting to - * clear the PM_WKST_x are detected and cleared. - */ -static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) -{ - u32 wkst, fclk, iclk, clken; - u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; - u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; - u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; - u16 grpsel_off = (regs == 3) ? - OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; - int c = 0; - - wkst = omap2_prm_read_mod_reg(module, wkst_off); - wkst &= omap2_prm_read_mod_reg(module, grpsel_off); - wkst &= ~ignore_bits; - if (wkst) { - iclk = omap2_cm_read_mod_reg(module, iclk_off); - fclk = omap2_cm_read_mod_reg(module, fclk_off); - while (wkst) { - clken = wkst; - omap2_cm_set_mod_reg_bits(clken, module, iclk_off); - /* - * For USBHOST, we don't know whether HOST1 or - * HOST2 woke us up, so enable both f-clocks - */ - if (module == OMAP3430ES2_USBHOST_MOD) - clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; - omap2_cm_set_mod_reg_bits(clken, module, fclk_off); - omap2_prm_write_mod_reg(wkst, module, wkst_off); - wkst = omap2_prm_read_mod_reg(module, wkst_off); - wkst &= ~ignore_bits; - c++; - } - omap2_cm_write_mod_reg(iclk, module, iclk_off); - omap2_cm_write_mod_reg(fclk, module, fclk_off); - } - - return c; -} - static irqreturn_t _prcm_int_handle_io(int irq, void *unused) { int c; - c = prcm_clear_mod_irqs(WKUP_MOD, 1, - ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); + c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, + ~(OMAP3430_ST_IO_MASK | + OMAP3430_ST_IO_CHAIN_MASK)); return c ? IRQ_HANDLED : IRQ_NONE; } @@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) * these are handled in a separate handler to avoid acking * IO events before parsing in mux code */ - c = prcm_clear_mod_irqs(WKUP_MOD, 1, - OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); - c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); - c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); + c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, + OMAP3430_ST_IO_MASK | + OMAP3430_ST_IO_CHAIN_MASK); + c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0); + c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); if (omap_rev() > OMAP3430_REV_ES1_0) { - c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); - c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); + c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0); + c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); } return c ? IRQ_HANDLED : IRQ_NONE; @@ -399,159 +353,11 @@ restore: #define omap3_pm_suspend NULL #endif /* CONFIG_SUSPEND */ - -/** - * omap3_iva_idle(): ensure IVA is in idle so it can be put into - * retention - * - * In cases where IVA2 is activated by bootcode, it may prevent - * full-chip retention or off-mode because it is not idle. This - * function forces the IVA2 into idle state so it can go - * into retention/off and thus allow full-chip retention/off. - * - **/ -static void __init omap3_iva_idle(void) -{ - /* ensure IVA2 clock is disabled */ - omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* if no clock activity, nothing else to do */ - if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & - OMAP3430_CLKACTIVITY_IVA2_MASK)) - return; - - /* Reset IVA2 */ - omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | - OMAP3430_RST2_IVA2_MASK | - OMAP3430_RST3_IVA2_MASK, - OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); - - /* Enable IVA2 clock */ - omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, - OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* Set IVA2 boot mode to 'idle' */ - omap3_ctrl_set_iva_bootmode_idle(); - - /* Un-reset IVA2 */ - omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); - - /* Disable IVA2 clock */ - omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); - - /* Reset IVA2 */ - omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | - OMAP3430_RST2_IVA2_MASK | - OMAP3430_RST3_IVA2_MASK, - OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); -} - -static void __init omap3_d2d_idle(void) -{ - u16 mask, padconf; - - /* In a stand alone OMAP3430 where there is not a stacked - * modem for the D2D Idle Ack and D2D MStandby must be pulled - * high. S CONTROL_PADCONF_SAD2D_IDLEACK and - * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ - mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ - padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); - padconf |= mask; - omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); - - padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); - padconf |= mask; - omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); - - /* reset modem */ - omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | - OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, - CORE_MOD, OMAP2_RM_RSTCTRL); - omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); -} - static void __init prcm_setup_regs(void) { - u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? - OMAP3630_EN_UART4_MASK : 0; - u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? - OMAP3630_GRPSEL_UART4_MASK : 0; - - /* XXX This should be handled by hwmod code or SCM init code */ - omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); - - /* - * Enable control of expternal oscillator through - * sys_clkreq. In the long run clock framework should - * take care of this. - */ - omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, - 1 << OMAP_AUTOEXTCLKMODE_SHIFT, - OMAP3430_GR_MOD, - OMAP3_PRM_CLKSRC_CTRL_OFFSET); - - /* setup wakup source */ - omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | - OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, - WKUP_MOD, PM_WKEN); - /* No need to write EN_IO, that is always enabled */ - omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | - OMAP3430_GRPSEL_GPT1_MASK | - OMAP3430_GRPSEL_GPT12_MASK, - WKUP_MOD, OMAP3430_PM_MPUGRPSEL); - - /* Enable PM_WKEN to support DSS LPR */ - omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, - OMAP3430_DSS_MOD, PM_WKEN); - - /* Enable wakeups in PER */ - omap2_prm_write_mod_reg(omap3630_en_uart4_mask | - OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | - OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | - OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | - OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | - OMAP3430_EN_MCBSP4_MASK, - OMAP3430_PER_MOD, PM_WKEN); - /* and allow them to wake up MPU */ - omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | - OMAP3430_GRPSEL_GPIO2_MASK | - OMAP3430_GRPSEL_GPIO3_MASK | - OMAP3430_GRPSEL_GPIO4_MASK | - OMAP3430_GRPSEL_GPIO5_MASK | - OMAP3430_GRPSEL_GPIO6_MASK | - OMAP3430_GRPSEL_UART3_MASK | - OMAP3430_GRPSEL_MCBSP2_MASK | - OMAP3430_GRPSEL_MCBSP3_MASK | - OMAP3430_GRPSEL_MCBSP4_MASK, - OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); - - /* Don't attach IVA interrupts */ - if (omap3_has_iva()) { - omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); - omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); - omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, - OMAP3430_PM_IVAGRPSEL); - } - - /* Clear any pending 'reset' flags */ - omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); - omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); - omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); - omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); - omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); - omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); - omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); - - /* Clear any pending PRCM interrupts */ - omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - - /* - * We need to idle iva2_pwrdm even on am3703 with no iva2. - */ - omap3_iva_idle(); + omap3_ctrl_init(); - omap3_d2d_idle(); + omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); } void omap3_pm_off_mode_enable(int enable) @@ -659,7 +465,7 @@ int __init omap3_pm_init(void) int ret; if (!omap3_has_io_chain_ctrl()) - pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); + pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); pm_errata_configure(); diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 0dda6cf8b855..503097c72b82 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -29,6 +29,7 @@ u16 pm44xx_errata; struct power_state { struct powerdomain *pwrdm; u32 next_state; + u32 next_logic_state; #ifdef CONFIG_SUSPEND u32 saved_state; u32 saved_logic_state; @@ -36,6 +37,8 @@ struct power_state { struct list_head node; }; +static u32 cpu_suspend_state = PWRDM_POWER_OFF; + static LIST_HEAD(pwrst_list); #ifdef CONFIG_SUSPEND @@ -54,7 +57,7 @@ static int omap4_pm_suspend(void) /* Set targeted power domain states by suspend */ list_for_each_entry(pwrst, &pwrst_list, node) { omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); - pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); + pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state); } /* @@ -66,7 +69,7 @@ static int omap4_pm_suspend(void) * domain CSWR is not supported by hardware. * More details can be found in OMAP4430 TRM section 4.3.4.2. */ - omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); + omap4_enter_lowpower(cpu_id, cpu_suspend_state); /* Restore next powerdomain state */ list_for_each_entry(pwrst, &pwrst_list, node) { @@ -112,15 +115,22 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) * through hotplug path and CPU0 explicitly programmed * further down in the code path */ - if (!strncmp(pwrdm->name, "cpu", 3)) + if (!strncmp(pwrdm->name, "cpu", 3)) { + if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) + cpu_suspend_state = PWRDM_POWER_RET; return 0; + } pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); if (!pwrst) return -ENOMEM; pwrst->pwrdm = pwrdm; - pwrst->next_state = PWRDM_POWER_RET; + pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false, + PWRDM_POWER_RET); + pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true, + PWRDM_POWER_OFF); + list_add(&pwrst->node, &pwrst_list); return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); @@ -203,6 +213,32 @@ static inline int omap4_init_static_deps(void) } /** + * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and + * DRA7 + * + * The dynamic dependency between MPUSS -> EMIF is broken and has + * not worked as expected. The hardware recommendation is to + * enable static dependencies for these to avoid system + * lock ups or random crashes. + */ +static inline int omap5_dra7_init_static_deps(void) +{ + struct clockdomain *mpuss_clkdm, *emif_clkdm; + int ret; + + mpuss_clkdm = clkdm_lookup("mpu_clkdm"); + emif_clkdm = clkdm_lookup("emif_clkdm"); + if (!mpuss_clkdm || !emif_clkdm) + return -EINVAL; + + ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); + if (ret) + pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n"); + + return ret; +} + +/** * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices * * Initializes basic stuff for power management functionality. @@ -212,6 +248,9 @@ int __init omap4_pm_init_early(void) if (cpu_is_omap446x()) pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; + if (soc_is_omap54xx() || soc_is_dra7xx()) + pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE; + return 0; } @@ -239,10 +278,14 @@ int __init omap4_pm_init(void) goto err2; } - if (cpu_is_omap44xx()) { + if (cpu_is_omap44xx()) ret = omap4_init_static_deps(); - if (ret) - goto err2; + else if (soc_is_omap54xx() || soc_is_dra7xx()) + ret = omap5_dra7_init_static_deps(); + + if (ret) { + pr_err("Failed to initialise static dependencies.\n"); + goto err2; } ret = omap4_mpuss_init(); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index faebd5f076af..7fb033eca0a5 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -546,7 +546,8 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, return -EINVAL; for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++) - ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); + if (pwrdm->pwrdm_clkdms[i]) + ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); return ret; } @@ -1080,6 +1081,82 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) } /** + * pwrdm_get_valid_lp_state() - Find best match deep power state + * @pwrdm: power domain for which we want to find best match + * @is_logic_state: Are we looking for logic state match here? Should + * be one of PWRDM_xxx macro values + * @req_state: requested power state + * + * Returns: closest match for requested power state. default fallback + * is RET for logic state and ON for power state. + * + * This does a search from the power domain data looking for the + * closest valid power domain state that the hardware can achieve. + * PRCM definitions for PWRSTCTRL allows us to program whatever + * configuration we'd like, and PRCM will actually attempt such + * a transition, however if the powerdomain does not actually support it, + * we endup with a hung system. The valid power domain states are already + * available in our powerdomain data files. So this function tries to do + * the following: + * a) find if we have an exact match to the request - no issues. + * b) else find if a deeper power state is possible. + * c) failing which, it tries to find closest higher power state for the + * request. + */ +u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm, + bool is_logic_state, u8 req_state) +{ + u8 pwrdm_states = is_logic_state ? pwrdm->pwrsts_logic_ret : + pwrdm->pwrsts; + /* For logic, ret is highest and others, ON is highest */ + u8 default_pwrst = is_logic_state ? PWRDM_POWER_RET : PWRDM_POWER_ON; + u8 new_pwrst; + bool found; + + /* If it is already supported, nothing to search */ + if (pwrdm_states & BIT(req_state)) + return req_state; + + if (!req_state) + goto up_search; + + /* + * So, we dont have a exact match + * Can we get a deeper power state match? + */ + new_pwrst = req_state - 1; + found = true; + while (!(pwrdm_states & BIT(new_pwrst))) { + /* No match even at OFF? Not available */ + if (new_pwrst == PWRDM_POWER_OFF) { + found = false; + break; + } + new_pwrst--; + } + + if (found) + goto done; + +up_search: + /* OK, no deeper ones, can we get a higher match? */ + new_pwrst = req_state + 1; + while (!(pwrdm_states & BIT(new_pwrst))) { + if (new_pwrst > PWRDM_POWER_ON) { + WARN(1, "powerdomain: %s: Fix max powerstate to ON\n", + pwrdm->name); + return PWRDM_POWER_ON; + } + + if (new_pwrst == default_pwrst) + break; + new_pwrst++; + } +done: + return new_pwrst; +} + +/** * omap_set_pwrdm_state - change a powerdomain's current power state * @pwrdm: struct powerdomain * to change the power state of * @pwrst: power state to change to diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index f4727117f6cc..11bd4dd7d8d6 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -39,6 +39,7 @@ #define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET) #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) +#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON) /* @@ -219,6 +220,9 @@ struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm); int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); +u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm, + bool is_logic_state, u8 req_state); + int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); int pwrdm_read_pwrst(struct powerdomain *pwrdm); diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c index ce1d752af991..60d7ed8ef8ca 100644 --- a/arch/arm/mach-omap2/powerdomains54xx_data.c +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c @@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = { .prcm_offs = OMAP54XX_PRM_CORE_INST, .prcm_partition = OMAP54XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* core_nret_bank */ @@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = { .voltdm = { .name = "mpu" }, .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ @@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = { .voltdm = { .name = "mpu" }, .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ @@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = { .prcm_offs = OMAP54XX_PRM_MPU_INST, .prcm_partition = OMAP54XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* mpu_l2 */ diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 48151d1cfde0..287a2037aa16 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -160,8 +160,8 @@ static struct powerdomain core_7xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = DRA7XX_PRM_CORE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_INA_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* core_nret_bank */ @@ -193,8 +193,8 @@ static struct powerdomain cpu0_7xx_pwrdm = { .name = "cpu0_pwrdm", .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ @@ -209,8 +209,8 @@ static struct powerdomain cpu1_7xx_pwrdm = { .name = "cpu1_pwrdm", .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ @@ -243,7 +243,7 @@ static struct powerdomain mpu_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_MPU_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* mpu_l2 */ diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index 7785be984edd..ad7b3e9977f8 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -142,5 +142,6 @@ #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 +#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 #endif diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c index a3a3cca2bcc4..86958050547a 100644 --- a/arch/arm/mach-omap2/prm2xxx.c +++ b/arch/arm/mach-omap2/prm2xxx.c @@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void) omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); } +/** + * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module + * @module: PRM module to clear wakeups from + * @regs: register offset to clear + * @wkst_mask: wakeup status mask to clear + * + * Clears wakeup status bits for a given module, so that the device can + * re-enter idle. + */ +void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask) +{ + u32 wkst; + + wkst = omap2_prm_read_mod_reg(module, regs); + wkst &= wkst_mask; + omap2_prm_write_mod_reg(wkst, module, regs); +} + int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) { omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h index d2cb6365716f..d73414139292 100644 --- a/arch/arm/mach-omap2/prm2xxx.h +++ b/arch/arm/mach-omap2/prm2xxx.h @@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); extern void omap2xxx_prm_dpll_reset(void); +void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); extern int __init omap2xxx_prm_init(void); diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 4bd7a2dca8af..ff08da385a2d 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -17,6 +17,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/of_irq.h> #include "soc.h" #include "common.h" @@ -26,6 +27,8 @@ #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" #include "prm-regbits-34xx.h" +#include "cm3xxx.h" +#include "cm-regbits-34xx.h" static const struct omap_prcm_irq omap3_prcm_irqs[] = { OMAP_PRCM_IRQ("wkup", 0, 0), @@ -43,7 +46,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { .ocp_barrier = &omap3xxx_prm_ocp_barrier, .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, .restore_irqen = &omap3xxx_prm_restore_irqen, - .reconfigure_io_chain = &omap3xxx_prm_reconfigure_io_chain, + .reconfigure_io_chain = NULL, }; /* @@ -206,15 +209,191 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask) } /** - * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain + * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt + * @module: PRM module to clear wakeups from + * @regs: register set to clear, 1 or 3 + * @ignore_bits: wakeup status bits to ignore + * + * The purpose of this function is to clear any wake-up events latched + * in the PRCM PM_WKST_x registers. It is possible that a wake-up event + * may occur whilst attempting to clear a PM_WKST_x register and thus + * set another bit in this register. A while loop is used to ensure + * that any peripheral wake-up events occurring while attempting to + * clear the PM_WKST_x are detected and cleared. + */ +int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) +{ + u32 wkst, fclk, iclk, clken; + u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; + u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; + u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; + u16 grpsel_off = (regs == 3) ? + OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; + int c = 0; + + wkst = omap2_prm_read_mod_reg(module, wkst_off); + wkst &= omap2_prm_read_mod_reg(module, grpsel_off); + wkst &= ~ignore_bits; + if (wkst) { + iclk = omap2_cm_read_mod_reg(module, iclk_off); + fclk = omap2_cm_read_mod_reg(module, fclk_off); + while (wkst) { + clken = wkst; + omap2_cm_set_mod_reg_bits(clken, module, iclk_off); + /* + * For USBHOST, we don't know whether HOST1 or + * HOST2 woke us up, so enable both f-clocks + */ + if (module == OMAP3430ES2_USBHOST_MOD) + clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; + omap2_cm_set_mod_reg_bits(clken, module, fclk_off); + omap2_prm_write_mod_reg(wkst, module, wkst_off); + wkst = omap2_prm_read_mod_reg(module, wkst_off); + wkst &= ~ignore_bits; + c++; + } + omap2_cm_write_mod_reg(iclk, module, iclk_off); + omap2_cm_write_mod_reg(fclk, module, fclk_off); + } + + return c; +} + +/** + * omap3_prm_reset_modem - toggle reset signal for modem + * + * Toggles the reset signal to modem IP block. Required to allow + * OMAP3430 without stacked modem to idle properly. + */ +void __init omap3_prm_reset_modem(void) +{ + omap2_prm_write_mod_reg( + OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | + OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, + CORE_MOD, OMAP2_RM_RSTCTRL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); +} + +/** + * omap3_prm_init_pm - initialize PM related registers for PRM + * @has_uart4: SoC has UART4 + * @has_iva: SoC has IVA + * + * Initializes PRM registers for PM use. Called from PM init. + */ +void __init omap3_prm_init_pm(bool has_uart4, bool has_iva) +{ + u32 en_uart4_mask; + u32 grpsel_uart4_mask; + + /* + * Enable control of expternal oscillator through + * sys_clkreq. In the long run clock framework should + * take care of this. + */ + omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, + 1 << OMAP_AUTOEXTCLKMODE_SHIFT, + OMAP3430_GR_MOD, + OMAP3_PRM_CLKSRC_CTRL_OFFSET); + + /* setup wakup source */ + omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | + OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, + WKUP_MOD, PM_WKEN); + /* No need to write EN_IO, that is always enabled */ + omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | + OMAP3430_GRPSEL_GPT1_MASK | + OMAP3430_GRPSEL_GPT12_MASK, + WKUP_MOD, OMAP3430_PM_MPUGRPSEL); + + /* Enable PM_WKEN to support DSS LPR */ + omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, + OMAP3430_DSS_MOD, PM_WKEN); + + if (has_uart4) { + en_uart4_mask = OMAP3630_EN_UART4_MASK; + grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK; + } + + /* Enable wakeups in PER */ + omap2_prm_write_mod_reg(en_uart4_mask | + OMAP3430_EN_GPIO2_MASK | + OMAP3430_EN_GPIO3_MASK | + OMAP3430_EN_GPIO4_MASK | + OMAP3430_EN_GPIO5_MASK | + OMAP3430_EN_GPIO6_MASK | + OMAP3430_EN_UART3_MASK | + OMAP3430_EN_MCBSP2_MASK | + OMAP3430_EN_MCBSP3_MASK | + OMAP3430_EN_MCBSP4_MASK, + OMAP3430_PER_MOD, PM_WKEN); + + /* and allow them to wake up MPU */ + omap2_prm_write_mod_reg(grpsel_uart4_mask | + OMAP3430_GRPSEL_GPIO2_MASK | + OMAP3430_GRPSEL_GPIO3_MASK | + OMAP3430_GRPSEL_GPIO4_MASK | + OMAP3430_GRPSEL_GPIO5_MASK | + OMAP3430_GRPSEL_GPIO6_MASK | + OMAP3430_GRPSEL_UART3_MASK | + OMAP3430_GRPSEL_MCBSP2_MASK | + OMAP3430_GRPSEL_MCBSP3_MASK | + OMAP3430_GRPSEL_MCBSP4_MASK, + OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); + + /* Don't attach IVA interrupts */ + if (has_iva) { + omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); + omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, + OMAP3430_PM_IVAGRPSEL); + } + + /* Clear any pending 'reset' flags */ + omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, + OMAP2_RM_RSTST); + + /* Clear any pending PRCM interrupts */ + omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + + /* We need to idle iva2_pwrdm even on am3703 with no iva2. */ + omap3xxx_prm_iva_idle(); + + omap3_prm_reset_modem(); +} + +/** + * omap3430_pre_es3_1_reconfigure_io_chain - restart wake-up daisy chain + * + * The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only + * thing we can do is toggle EN_IO bit for earlier omaps. + */ +void omap3430_pre_es3_1_reconfigure_io_chain(void) +{ + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, + PM_WKEN); + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, + PM_WKEN); + omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); +} + +/** + * omap3_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain * * Clear any previously-latched I/O wakeup events and ensure that the * I/O wakeup gates are aligned with the current mux settings. Works * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No - * return value. + * return value. These registers are only available in 3430 es3.1 and later. */ -void omap3xxx_prm_reconfigure_io_chain(void) +void omap3_prm_reconfigure_io_chain(void) { int i = 0; @@ -237,6 +416,15 @@ void omap3xxx_prm_reconfigure_io_chain(void) } /** + * omap3xxx_prm_reconfigure_io_chain - reconfigure I/O chain + */ +void omap3xxx_prm_reconfigure_io_chain(void) +{ + if (omap3_prcm_irq_setup.reconfigure_io_chain) + omap3_prcm_irq_setup.reconfigure_io_chain(); +} + +/** * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches * * Activates the I/O wakeup event latches and allows events logged by @@ -276,6 +464,76 @@ static u32 omap3xxx_prm_read_reset_sources(void) return r; } +/** + * omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention + * + * In cases where IVA2 is activated by bootcode, it may prevent + * full-chip retention or off-mode because it is not idle. This + * function forces the IVA2 into idle state so it can go + * into retention/off and thus allow full-chip retention/off. + */ +void omap3xxx_prm_iva_idle(void) +{ + /* ensure IVA2 clock is disabled */ + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + + /* if no clock activity, nothing else to do */ + if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & + OMAP3430_CLKACTIVITY_IVA2_MASK)) + return; + + /* Reset IVA2 */ + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + OMAP3430_RST2_IVA2_MASK | + OMAP3430_RST3_IVA2_MASK, + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + + /* Enable IVA2 clock */ + omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, + OMAP3430_IVA2_MOD, CM_FCLKEN); + + /* Un-reset IVA2 */ + omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + + /* Disable IVA2 clock */ + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + + /* Reset IVA2 */ + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + OMAP3430_RST2_IVA2_MASK | + OMAP3430_RST3_IVA2_MASK, + OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); +} + +/** + * omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status + * and clears it if asserted + * + * Checks if cold-reset has occurred and clears the status bit if yes. Returns + * 1 if cold-reset has occurred, 0 otherwise. + */ +int omap3xxx_prm_clear_global_cold_reset(void) +{ + if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & + OMAP3430_GLOBAL_COLD_RST_MASK) { + omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, + OMAP3430_GR_MOD, + OMAP3_PRM_RSTST_OFFSET); + return 1; + } + + return 0; +} + +void omap3_prm_save_scratchpad_contents(u32 *ptr) +{ + *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, + OMAP3_PRM_CLKSRC_CTRL_OFFSET); + + *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, + OMAP3_PRM_CLKSEL_OFFSET); +} + /* Powerdomain low-level functions */ static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) @@ -416,6 +674,11 @@ int __init omap3xxx_prm_init(void) return prm_register(&omap3xxx_prm_ll_data); } +static struct of_device_id omap3_prm_dt_match_table[] = { + { .compatible = "ti,omap3-prm" }, + { } +}; + static int omap3xxx_prm_late_init(void) { int ret; @@ -423,6 +686,25 @@ static int omap3xxx_prm_late_init(void) if (!(prm_features & PRM_HAS_IO_WAKEUP)) return 0; + if (omap3_has_io_chain_ctrl()) + omap3_prcm_irq_setup.reconfigure_io_chain = + omap3_prm_reconfigure_io_chain; + else + omap3_prcm_irq_setup.reconfigure_io_chain = + omap3430_pre_es3_1_reconfigure_io_chain; + + if (of_have_populated_dt()) { + struct device_node *np; + int irq_num; + + np = of_find_matching_node(NULL, omap3_prm_dt_match_table); + if (np) { + irq_num = of_irq_get(np, 0); + if (irq_num >= 0) + omap3_prcm_irq_setup.irq = irq_num; + } + } + omap3xxx_prm_enable_io_wakeup(); ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); if (!ret) diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h index 1dacfc5b1959..bc37d42a8704 100644 --- a/arch/arm/mach-omap2/prm3xxx.h +++ b/arch/arm/mach-omap2/prm3xxx.h @@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void); extern int __init omap3xxx_prm_init(void); extern u32 omap3xxx_prm_get_reset_sources(void); +int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits); +void omap3xxx_prm_iva_idle(void); +void omap3_prm_reset_modem(void); +int omap3xxx_prm_clear_global_cold_reset(void); +void omap3_prm_save_scratchpad_contents(u32 *ptr); +void omap3_prm_init_pm(bool has_uart4, bool has_iva); #endif /* __ASSEMBLER */ diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index a7f6ea27180a..0958d070d3db 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -17,6 +17,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/of_irq.h> #include "soc.h" @@ -32,7 +33,6 @@ /* Static data */ static const struct omap_prcm_irq omap4_prcm_irqs[] = { - OMAP_PRCM_IRQ("wkup", 0, 0), OMAP_PRCM_IRQ("io", 9, 1), }; @@ -154,21 +154,36 @@ void omap4_prm_vp_clear_txdone(u8 vp_id) u32 omap4_prm_vcvp_read(u8 offset) { + s32 inst = omap4_prmst_get_prm_dev_inst(); + + if (inst == PRM_INSTANCE_UNKNOWN) + return 0; + return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, - OMAP4430_PRM_DEVICE_INST, offset); + inst, offset); } void omap4_prm_vcvp_write(u32 val, u8 offset) { + s32 inst = omap4_prmst_get_prm_dev_inst(); + + if (inst == PRM_INSTANCE_UNKNOWN) + return; + omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, - OMAP4430_PRM_DEVICE_INST, offset); + inst, offset); } u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) { + s32 inst = omap4_prmst_get_prm_dev_inst(); + + if (inst == PRM_INSTANCE_UNKNOWN) + return 0; + return omap4_prminst_rmw_inst_reg_bits(mask, bits, OMAP4430_PRM_PARTITION, - OMAP4430_PRM_DEVICE_INST, + inst, offset); } @@ -275,14 +290,18 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask) void omap44xx_prm_reconfigure_io_chain(void) { int i = 0; + s32 inst = omap4_prmst_get_prm_dev_inst(); + + if (inst == PRM_INSTANCE_UNKNOWN) + return; /* Trigger WUCLKIN enable */ omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, OMAP4430_WUCLK_CTRL_MASK, - OMAP4430_PRM_DEVICE_INST, + inst, OMAP4_PRM_IO_PMCTRL_OFFSET); omap_test_timeout( - (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + (((omap4_prm_read_inst_reg(inst, OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_WUCLK_STATUS_MASK) >> OMAP4430_WUCLK_STATUS_SHIFT) == 1), @@ -292,10 +311,10 @@ void omap44xx_prm_reconfigure_io_chain(void) /* Trigger WUCLKIN disable */ omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, - OMAP4430_PRM_DEVICE_INST, + inst, OMAP4_PRM_IO_PMCTRL_OFFSET); omap_test_timeout( - (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + (((omap4_prm_read_inst_reg(inst, OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_WUCLK_STATUS_MASK) >> OMAP4430_WUCLK_STATUS_SHIFT) == 0), @@ -316,9 +335,14 @@ void omap44xx_prm_reconfigure_io_chain(void) */ static void __init omap44xx_prm_enable_io_wakeup(void) { + s32 inst = omap4_prmst_get_prm_dev_inst(); + + if (inst == PRM_INSTANCE_UNKNOWN) + return; + omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_GLOBAL_WUEN_MASK, - OMAP4430_PRM_DEVICE_INST, + inst, OMAP4_PRM_IO_PMCTRL_OFFSET); } @@ -333,8 +357,13 @@ static u32 omap44xx_prm_read_reset_sources(void) struct prm_reset_src_map *p; u32 r = 0; u32 v; + s32 inst = omap4_prmst_get_prm_dev_inst(); - v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + if (inst == PRM_INSTANCE_UNKNOWN) + return 0; + + + v = omap4_prm_read_inst_reg(inst, OMAP4_RM_RSTST); p = omap44xx_prm_reset_src_map; @@ -664,17 +693,56 @@ static struct prm_ll_data omap44xx_prm_ll_data = { int __init omap44xx_prm_init(void) { - if (cpu_is_omap44xx()) + if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) prm_features |= PRM_HAS_IO_WAKEUP; return prm_register(&omap44xx_prm_ll_data); } +static struct of_device_id omap_prm_dt_match_table[] = { + { .compatible = "ti,omap4-prm" }, + { .compatible = "ti,omap5-prm" }, + { .compatible = "ti,dra7-prm" }, + { } +}; + static int omap44xx_prm_late_init(void) { + struct device_node *np; + int irq_num; + if (!(prm_features & PRM_HAS_IO_WAKEUP)) return 0; + /* OMAP4+ is DT only now */ + if (!of_have_populated_dt()) + return 0; + + np = of_find_matching_node(NULL, omap_prm_dt_match_table); + + if (!np) { + /* Default loaded up with OMAP4 values */ + if (!cpu_is_omap44xx()) + return 0; + } else { + irq_num = of_irq_get(np, 0); + /* + * Already have OMAP4 IRQ num. For all other platforms, we need + * IRQ numbers from DT + */ + if (irq_num < 0 && !cpu_is_omap44xx()) { + if (irq_num == -EPROBE_DEFER) + return irq_num; + + /* Have nothing to do */ + return 0; + } + + /* Once OMAP4 DT is filled as well */ + if (irq_num >= 0) + omap4_prcm_irq_setup.irq = irq_num; + } + omap44xx_prm_enable_io_wakeup(); return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h index d92a8404edc7..4bb50fbf29be 100644 --- a/arch/arm/mach-omap2/prm7xx.h +++ b/arch/arm/mach-omap2/prm7xx.h @@ -374,6 +374,10 @@ #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c +#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0 +#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4 +#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8 +#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 25e8b8232115..ee2b5222eac0 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -467,11 +467,13 @@ int prm_unregister(struct prm_ll_data *pld) return 0; } -static struct of_device_id omap_prcm_dt_match_table[] = { +static const struct of_device_id omap_prcm_dt_match_table[] = { { .compatible = "ti,am3-prcm" }, { .compatible = "ti,am3-scrm" }, { .compatible = "ti,am4-prcm" }, { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap2-prcm" }, + { .compatible = "ti,omap2-scrm" }, { .compatible = "ti,omap3-prm" }, { .compatible = "ti,omap3-cm" }, { .compatible = "ti,omap3-scrm" }, @@ -523,8 +525,6 @@ int __init of_prcm_init(void) memmap_index++; } - ti_dt_clockdomains_setup(); - return 0; } diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index 69f0dd08629c..225e0258d76d 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -31,6 +31,8 @@ static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; +static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN; + /** * omap_prm_base_init - Populates the prm partitions * @@ -43,6 +45,24 @@ void omap_prm_base_init(void) _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; } +s32 omap4_prmst_get_prm_dev_inst(void) +{ + if (prm_dev_inst != PRM_INSTANCE_UNKNOWN) + return prm_dev_inst; + + /* This cannot be done way early at boot.. as things are not setup */ + if (cpu_is_omap44xx()) + prm_dev_inst = OMAP4430_PRM_DEVICE_INST; + else if (soc_is_omap54xx()) + prm_dev_inst = OMAP54XX_PRM_DEVICE_INST; + else if (soc_is_dra7xx()) + prm_dev_inst = DRA7XX_PRM_DEVICE_INST; + else if (soc_is_am43xx()) + prm_dev_inst = AM43XX_PRM_DEVICE_INST; + + return prm_dev_inst; +} + /* Read a register in a PRM instance */ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) { @@ -169,28 +189,18 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst, void omap4_prminst_global_warm_sw_reset(void) { u32 v; - s16 dev_inst; + s32 inst = omap4_prmst_get_prm_dev_inst(); - if (cpu_is_omap44xx()) - dev_inst = OMAP4430_PRM_DEVICE_INST; - else if (soc_is_omap54xx()) - dev_inst = OMAP54XX_PRM_DEVICE_INST; - else if (soc_is_dra7xx()) - dev_inst = DRA7XX_PRM_DEVICE_INST; - else if (soc_is_am43xx()) - dev_inst = AM43XX_PRM_DEVICE_INST; - else + if (inst == PRM_INSTANCE_UNKNOWN) return; - v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst, + v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst, OMAP4_PRM_RSTCTRL_OFFSET); v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, - dev_inst, - OMAP4_PRM_RSTCTRL_OFFSET); + inst, OMAP4_PRM_RSTCTRL_OFFSET); /* OCP barrier */ v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, - dev_inst, - OMAP4_PRM_RSTCTRL_OFFSET); + inst, OMAP4_PRM_RSTCTRL_OFFSET); } diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h index a2ede2d65481..583aa3774571 100644 --- a/arch/arm/mach-omap2/prminst44xx.h +++ b/arch/arm/mach-omap2/prminst44xx.h @@ -12,6 +12,9 @@ #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H #define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H +#define PRM_INSTANCE_UNKNOWN -1 +extern s32 omap4_prmst_get_prm_dev_inst(void); + /* * In an ideal world, we would not export these low-level functions, * but this will probably take some time to fix properly diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c index 7a42e1960c3b..d3a588cf3a6e 100644 --- a/arch/arm/mach-omap2/smartreflex-class3.c +++ b/arch/arm/mach-omap2/smartreflex-class3.c @@ -20,8 +20,8 @@ static int sr_class3_enable(struct omap_sr *sr) unsigned long volt = voltdm_get_voltage(sr->voltdm); if (!volt) { - pr_warning("%s: Curr voltage unknown. Cannot enable %s\n", - __func__, sr->name); + pr_warn("%s: Curr voltage unknown. Cannot enable %s\n", + __func__, sr->name); return -ENODATA; } diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 01ca8086fb6c..4376f59626d1 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -245,6 +245,8 @@ IS_AM_SUBCLASS(437x, 0x437) #define soc_is_omap54xx() 0 #define soc_is_omap543x() 0 #define soc_is_dra7xx() 0 +#define soc_is_dra74x() 0 +#define soc_is_dra72x() 0 #if defined(MULTI_OMAP2) # if defined(CONFIG_ARCH_OMAP2) @@ -393,7 +395,11 @@ IS_OMAP_TYPE(3430, 0x3430) #if defined(CONFIG_SOC_DRA7XX) #undef soc_is_dra7xx +#undef soc_is_dra74x +#undef soc_is_dra72x #define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) +#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74")) +#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72")) #endif /* Various silicon revisions for omap2 */ diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index 1b91ef0c182a..d7cff2632d1e 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -154,7 +154,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data)); if (IS_ERR(pdev)) - pr_warning("%s: Could not build omap_device for %s: %s.\n\n", + pr_warn("%s: Could not build omap_device for %s: %s\n", __func__, name, oh->name); exit: i++; diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c index ddf1818af228..cd488b80ba36 100644 --- a/arch/arm/mach-omap2/sram.c +++ b/arch/arm/mach-omap2/sram.c @@ -32,12 +32,6 @@ #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) -#ifdef CONFIG_OMAP4_ERRATA_I688 -#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA -#else -#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) -#endif -#define OMAP5_SRAM_PA 0x40300000 #define SRAM_BOOTLOADER_SZ 0x00 @@ -105,32 +99,14 @@ static void __init omap_detect_sram(void) } else { omap_sram_size = 0x8000; /* 32K */ } - } else if (cpu_is_omap44xx()) { - omap_sram_start = OMAP4_SRAM_PUB_PA; - omap_sram_size = 0xa000; /* 40K */ - } else if (soc_is_omap54xx()) { - omap_sram_start = OMAP5_SRAM_PA; - omap_sram_size = SZ_128K; /* 128KB */ } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ } } else { - if (soc_is_am33xx()) { - omap_sram_start = AM33XX_SRAM_PA; - omap_sram_size = 0x10000; /* 64K */ - } else if (soc_is_am43xx()) { - omap_sram_start = AM33XX_SRAM_PA; - omap_sram_size = SZ_256K; - } else if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ - } else if (cpu_is_omap44xx()) { - omap_sram_start = OMAP4_SRAM_PA; - omap_sram_size = 0xe000; /* 56K */ - } else if (soc_is_omap54xx()) { - omap_sram_start = OMAP5_SRAM_PA; - omap_sram_size = SZ_128K; /* 128KB */ } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) @@ -148,12 +124,6 @@ static void __init omap2_map_sram(void) { int cached = 1; -#ifdef CONFIG_OMAP4_ERRATA_I688 - if (cpu_is_omap44xx()) { - omap_sram_start += PAGE_SIZE; - omap_sram_size -= SZ_16K; - } -#endif if (cpu_is_omap34xx()) { /* * SRAM must be marked as non-cached on OMAP3 since the @@ -285,11 +255,6 @@ static inline int omap34xx_sram_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -static inline int am33xx_sram_init(void) -{ - return 0; -} - int __init omap_sram_init(void) { omap_detect_sram(); @@ -299,8 +264,6 @@ int __init omap_sram_init(void) omap242x_sram_init(); else if (cpu_is_omap2430()) omap243x_sram_init(); - else if (soc_is_am33xx()) - am33xx_sram_init(); else if (cpu_is_omap34xx()) omap34xx_sram_init(); diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h index ca7277c2a9ee..948d3edefc38 100644 --- a/arch/arm/mach-omap2/sram.h +++ b/arch/arm/mach-omap2/sram.h @@ -74,10 +74,3 @@ static inline void omap_push_sram_idle(void) {} */ #define OMAP2_SRAM_PA 0x40200000 #define OMAP3_SRAM_PA 0x40200000 -#ifdef CONFIG_OMAP4_ERRATA_I688 -#define OMAP4_SRAM_PA 0x40304000 -#define OMAP4_SRAM_VA 0xfe404000 -#else -#define OMAP4_SRAM_PA 0x40300000 -#endif -#define AM33XX_SRAM_PA 0x40300000 diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 43d03fbf4c0b..4f61148ec168 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -141,7 +141,7 @@ static struct property device_disabled = { .value = "disabled", }; -static struct of_device_id omap_timer_match[] __initdata = { +static const struct of_device_id omap_timer_match[] __initconst = { { .compatible = "ti,omap2420-timer", }, { .compatible = "ti,omap3430-timer", }, { .compatible = "ti,omap4430-timer", }, @@ -162,7 +162,7 @@ static struct of_device_id omap_timer_match[] __initdata = { * the timer node in device-tree as disabled, to prevent the kernel from * registering this timer as a platform device and so no one else can use it. */ -static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, +static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, const char *property) { struct device_node *np; @@ -388,7 +388,7 @@ static u64 notrace dmtimer_read_sched_clock(void) return 0; } -static struct of_device_id omap_counter_match[] __initdata = { +static const struct of_device_id omap_counter_match[] __initconst = { { .compatible = "ti,omap-counter32k", }, { } }; diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index e832bc7b8e2d..8333400898fb 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -95,7 +95,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps) dev_t.t_avdp_w = t_scsnh_advnh; dev_t.cyc_aavdh_we = 3; dev_t.cyc_wpl = 6; - dev_t.t_ce_rdyz = 7000; gpmc_calc_timings(&t, &tusb_sync, &dev_t); diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index a4628a9e760c..be9ef834fa81 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -198,7 +198,7 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm, loop_cnt++; if (retries_cnt > 10) { - pr_warning("%s: Retry count exceeded\n", __func__); + pr_warn("%s: Retry count exceeded\n", __func__); return -ETIMEDOUT; } diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 3ac8fe1d8213..3783b8625f0f 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -55,7 +55,7 @@ static LIST_HEAD(voltdm_list); unsigned long voltdm_get_voltage(struct voltagedomain *voltdm) { if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); + pr_warn("%s: VDD specified does not exist!\n", __func__); return 0; } @@ -77,7 +77,7 @@ int voltdm_scale(struct voltagedomain *voltdm, unsigned long volt = 0; if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); + pr_warn("%s: VDD specified does not exist!\n", __func__); return -EINVAL; } @@ -96,8 +96,8 @@ int voltdm_scale(struct voltagedomain *voltdm, } if (!volt) { - pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n", - __func__, target_volt); + pr_warn("%s: not scaling. OPP voltage for %lu, not found.\n", + __func__, target_volt); return -EINVAL; } @@ -122,7 +122,7 @@ void voltdm_reset(struct voltagedomain *voltdm) unsigned long target_volt; if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); + pr_warn("%s: VDD specified does not exist!\n", __func__); return; } @@ -152,7 +152,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm, struct omap_volt_data **volt_data) { if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); + pr_warn("%s: VDD specified does not exist!\n", __func__); return; } @@ -180,12 +180,12 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, int i; if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); + pr_warn("%s: VDD specified does not exist!\n", __func__); return ERR_PTR(-EINVAL); } if (!voltdm->volt_data) { - pr_warning("%s: voltage table does not exist for vdd_%s\n", + pr_warn("%s: voltage table does not exist for vdd_%s\n", __func__, voltdm->name); return ERR_PTR(-ENODATA); } @@ -214,7 +214,7 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm, struct omap_voltdm_pmic *pmic) { if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); + pr_warn("%s: VDD specified does not exist!\n", __func__); return -EINVAL; } @@ -237,7 +237,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm, int voltscale_method) { if (!voltdm || IS_ERR(voltdm)) { - pr_warning("%s: VDD specified does not exist!\n", __func__); + pr_warn("%s: VDD specified does not exist!\n", __func__); return; } @@ -279,7 +279,7 @@ int __init omap_voltage_late_init(void) sys_ck = clk_get(NULL, voltdm->sys_clk.name); if (IS_ERR(sys_ck)) { - pr_warning("%s: Could not get sys clk.\n", __func__); + pr_warn("%s: Could not get sys clk.\n", __func__); return -EINVAL; } voltdm->sys_clk.rate = clk_get_rate(sys_ck); diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c index 97d6607d447a..ff0a68cf7439 100644 --- a/arch/arm/mach-omap2/wd_timer.c +++ b/arch/arm/mach-omap2/wd_timer.c @@ -93,8 +93,8 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh) udelay(oh->class->sysc->srst_udelay); if (c == MAX_MODULE_SOFTRESET_WAIT) - pr_warning("%s: %s: softreset failed (waited %d usec)\n", - __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); + pr_warn("%s: %s: softreset failed (waited %d usec)\n", + __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); else pr_debug("%s: %s: softreset in %d usec\n", __func__, oh->name, c); |