diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-03-17 17:53:31 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-30 01:49:40 +0200 |
| commit | deb125abad130fc1200782048a79079f5a41af05 (patch) | |
| tree | 59a72c115c1d78ad1f44a3c5f0c5689fdffcb61d /arch/arm/mach-omap2 | |
| parent | ARM: l2c: omap2: remove explicit SMI calls to enable L2 cache (diff) | |
| download | linux-deb125abad130fc1200782048a79079f5a41af05.tar.xz linux-deb125abad130fc1200782048a79079f5a41af05.zip | |
ARM: l2c: omap2: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/omap4-common.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 9ce52548a484..06c6a181d6ad 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -213,20 +213,18 @@ static int __init omap_l2_cache_init(void) return -ENOMEM; /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ - aux_ctrl = L310_AUX_CTRL_ASSOCIATIVITY_16 | - L310_AUX_CTRL_CACHE_REPLACE_RR | + aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR | L310_AUX_CTRL_NS_LOCKDOWN | L310_AUX_CTRL_NS_INT_CTRL | - L2C_AUX_CTRL_WAY_SIZE(3) | L2C_AUX_CTRL_SHARED_OVERRIDE | L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH; outer_cache.write_sec = omap4_l2c310_write_sec; if (of_have_populated_dt()) - l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); + l2x0_of_init(aux_ctrl, 0xc19fffff); else - l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); + l2x0_init(l2cache_base, aux_ctrl, 0xc19fffff); return 0; } |