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| author | Philipp Zabel <p.zabel@pengutronix.de> | 2014-02-24 14:51:50 +0100 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-03-05 03:40:48 +0100 |
| commit | 7ea653efa98d8144345227576fc084ed7a356cf8 (patch) | |
| tree | c749da48570ce6b0554608eb2aed982468602fa0 /arch/arm/mach-pxa/colibri-pxa3xx.c | |
| parent | ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr (diff) | |
| download | linux-7ea653efa98d8144345227576fc084ed7a356cf8.tar.xz linux-7ea653efa98d8144345227576fc084ed7a356cf8.zip | |
ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
This is needed so that the IPU framebuffer scanout cannot be
starved by VPU or GPU activity.
Some boards like the SabreLite and SabreSD seem to set this in
the DCD already, but the documented register reset values do not
contain the necessary settings.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-pxa/colibri-pxa3xx.c')
0 files changed, 0 insertions, 0 deletions