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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-30 05:04:53 +0200 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-30 05:04:53 +0200 |
| commit | 9ff9a26b786c35ee8d2a66222924a807ec851a9f (patch) | |
| tree | db432a17bccca1ca2c16907f0ee83ac449ed4012 /arch/arm/mach-pxa/include/mach/regs-ost.h | |
| parent | Merge commit 'kumar/next' into next (diff) | |
| parent | Merge branch 'bzip2-lzma-for-linus' of git://git.kernel.org/pub/scm/linux/ker... (diff) | |
| download | linux-9ff9a26b786c35ee8d2a66222924a807ec851a9f.tar.xz linux-9ff9a26b786c35ee8d2a66222924a807ec851a9f.zip | |
Merge commit 'origin/master' into next
Manual merge of:
arch/powerpc/include/asm/elf.h
drivers/i2c/busses/i2c-mpc.c
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/regs-ost.h')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-ost.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h new file mode 100644 index 000000000000..a3e5f86ef67e --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -0,0 +1,34 @@ +#ifndef __ASM_MACH_REGS_OST_H +#define __ASM_MACH_REGS_OST_H + +#include <mach/hardware.h> + +/* + * OS Timer & Match Registers + */ + +#define OSMR0 __REG(0x40A00000) /* */ +#define OSMR1 __REG(0x40A00004) /* */ +#define OSMR2 __REG(0x40A00008) /* */ +#define OSMR3 __REG(0x40A0000C) /* */ +#define OSMR4 __REG(0x40A00080) /* */ +#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ +#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 __REG(0x40A000C0) /* */ +#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ +#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ + +#define OSSR_M3 (1 << 3) /* Match status channel 3 */ +#define OSSR_M2 (1 << 2) /* Match status channel 2 */ +#define OSSR_M1 (1 << 1) /* Match status channel 1 */ +#define OSSR_M0 (1 << 0) /* Match status channel 0 */ + +#define OWER_WME (1 << 0) /* Watchdog Match Enable */ + +#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ +#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ +#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ +#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ + +#endif /* __ASM_MACH_REGS_OST_H */ |