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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2009-05-09 03:29:27 +0200 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2009-05-09 03:29:27 +0200 |
| commit | d585a021c0b10b0477d6b608c53e1feb8cde0507 (patch) | |
| tree | 5ca059da1db7f15d4b29427644ad9c08270c885c /arch/arm/mach-pxa/include/mach/regs-ost.h | |
| parent | Input: wm97xx - do not access dev->driver_data directly (diff) | |
| parent | Linux 2.6.30-rc5 (diff) | |
| download | linux-d585a021c0b10b0477d6b608c53e1feb8cde0507.tar.xz linux-d585a021c0b10b0477d6b608c53e1feb8cde0507.zip | |
Merge commit 'v2.6.30-rc5' into next
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/regs-ost.h')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-ost.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h new file mode 100644 index 000000000000..a3e5f86ef67e --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -0,0 +1,34 @@ +#ifndef __ASM_MACH_REGS_OST_H +#define __ASM_MACH_REGS_OST_H + +#include <mach/hardware.h> + +/* + * OS Timer & Match Registers + */ + +#define OSMR0 __REG(0x40A00000) /* */ +#define OSMR1 __REG(0x40A00004) /* */ +#define OSMR2 __REG(0x40A00008) /* */ +#define OSMR3 __REG(0x40A0000C) /* */ +#define OSMR4 __REG(0x40A00080) /* */ +#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ +#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 __REG(0x40A000C0) /* */ +#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ +#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ + +#define OSSR_M3 (1 << 3) /* Match status channel 3 */ +#define OSSR_M2 (1 << 2) /* Match status channel 2 */ +#define OSSR_M1 (1 << 1) /* Match status channel 1 */ +#define OSSR_M0 (1 << 0) /* Match status channel 0 */ + +#define OWER_WME (1 << 0) /* Watchdog Match Enable */ + +#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ +#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ +#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ +#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ + +#endif /* __ASM_MACH_REGS_OST_H */ |