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| author | Heiko Stuebner <heiko@sntech.de> | 2013-02-12 19:12:09 +0100 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-03-05 12:21:31 +0100 |
| commit | 1c8408e3137bcb78d9ab8af832111f455d11e99c (patch) | |
| tree | 35d1896ca67c6f007179256678754243e63a97e6 /arch/arm/mach-s3c24xx/include | |
| parent | ARM: S3C24XX: add soc_is_s3c2412 option (diff) | |
| download | linux-1c8408e3137bcb78d9ab8af832111f455d11e99c.tar.xz linux-1c8408e3137bcb78d9ab8af832111f455d11e99c.zip | |
ARM: S3C24XX: handle s3c2412 eints using new infrastructure
The s3c2412 handles the eints 0 to 3 different than all the other SoCs
of the 24xx range. These eints must be acked and masked in the regular
bits as well as the bits 0 to 3 of the eint registers, which are unused
on the other SoCs.
This of course can be realized using the new infrastructure with the
eint bits in the main register being the parent interrupts of the
same bits in the eint register.
The s3c2412 therefore gets its own IRQ_EINT0 to 4 constants that
reside in the newly created gap before IRQ_EINT4. gpio-samsung, as the
only user of these is modified to return the correct values when
handling gpio_to_irq requests on s3c2412 based machines.
Due to lack of hardware this is compile tested only, but should
hopefully work as intended.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx/include')
| -rw-r--r-- | arch/arm/mach-s3c24xx/include/mach/irqs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h index ea589e4f0d8b..43cada8019b4 100644 --- a/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h @@ -59,6 +59,10 @@ #define IRQ_ADCPARENT S3C2410_IRQ(31) /* interrupts generated from the external interrupts sources */ +#define IRQ_EINT0_2412 S3C2410_IRQ(32) +#define IRQ_EINT1_2412 S3C2410_IRQ(33) +#define IRQ_EINT2_2412 S3C2410_IRQ(34) +#define IRQ_EINT3_2412 S3C2410_IRQ(35) #define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ #define IRQ_EINT5 S3C2410_IRQ(37) #define IRQ_EINT6 S3C2410_IRQ(38) |