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author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-09 23:30:28 +0100 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-09 23:30:28 +0100 |
commit | 190a44e65b0f32eaf5b4db3969f5eb224f83a7a2 (patch) | |
tree | 577c9a3949ba06e62d082eb11894b7045ebe3ef3 /arch/arm/mach-s5p64x0/clock-s5p6440.c | |
parent | Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc (diff) | |
parent | Merge branch 'samsung/cleanup' into next/cleanup2 (diff) | |
download | linux-190a44e65b0f32eaf5b4db3969f5eb224f83a7a2.tar.xz linux-190a44e65b0f32eaf5b4db3969f5eb224f83a7a2.zip |
Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Cleanups for the Samsung platforms
Various cleanup changes that the device driver changes are built upon.
Since the samsung cleanups depend on the device tree series, which
depends on the first set of cleanups for tegra.
* tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: EXYNOS: Use gpio_request_one
ARM: S5PV210: Use gpio_request_one
ARM: S3C64XX: Modified according to SPI consolidation work
ARM: S5PV210: Modified files for SPI consolidation work
ARM: S5P64X0: Modified files for SPI consolidation work
ARM: S5PC100: Modified files for SPI consolidation work
ARM: S3C64XX: Modified files for SPI consolidation work
ARM: SAMSUNG: Consolidation of SPI platform devices to plat-samsung
ARM: SAMSUNG: Remove SPI bus clocks from platform data
ARM: S5PV210: Add SPI clkdev support
ARM: S5P64X0: Add SPI clkdev support
ARM: S5PC100: Add SPI clkdev support
ARM: S3C64XX: Add SPI clkdev support
spi/s3c64xx: Use bus clocks created using clkdev
mmc: sdhci-s3c: Use generic clock names for sdhci bus clock options
ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
ARM: SAMSUNG: Remove SDHCI bus clocks from platform data
ARM: SAMSUNG: Use kmemdup rather than duplicating its implementation
ARM: EXYNOS: remove exynos4_scu_enable()
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock-s5p6440.c')
-rw-r--r-- | arch/arm/mach-s5p64x0/clock-s5p6440.c | 61 |
1 files changed, 29 insertions, 32 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 4c797ab3b3fd..925d2daa60c7 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -269,18 +269,6 @@ static struct clk init_clocks_off[] = { .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 31), }, { - .name = "sclk_spi_48", - .devname = "s3c64xx-spi.0", - .parent = &clk_48m, - .enable = s5p64x0_sclk_ctrl, - .ctrlbit = (1 << 22), - }, { - .name = "sclk_spi_48", - .devname = "s3c64xx-spi.1", - .parent = &clk_48m, - .enable = s5p64x0_sclk_ctrl, - .ctrlbit = (1 << 23), - }, { .name = "mmc_48m", .devname = "s3c-sdhci.0", .parent = &clk_48m, @@ -422,26 +410,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, }, { .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .ctrlbit = (1 << 20), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group1, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .ctrlbit = (1 << 21), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group1, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, - }, { - .clk = { .name = "sclk_post", .ctrlbit = (1 << 10), .enable = s5p64x0_sclk_ctrl, @@ -490,6 +458,30 @@ static struct clksrc_clk clk_sclk_uclk = { .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, }; +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.0", + .ctrlbit = (1 << 20), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.1", + .ctrlbit = (1 << 21), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, +}; + /* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -510,11 +502,16 @@ static struct clk dummy_apb_pclk = { static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uclk, + &clk_sclk_spi0, + &clk_sclk_spi1, }; static struct clk_lookup s5p6440_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), }; void __init_or_cpufreq s5p6440_setup_clocks(void) |