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| author | Thomas Gleixner <tglx@linutronix.de> | 2010-12-09 18:17:25 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2010-12-09 18:17:25 +0100 |
| commit | d834a9dcecae834cd6b2bc5e50e1907738d9cf6a (patch) | |
| tree | 0589d753465d3fe359ba451ba6cb7798df03aaa2 /arch/arm/mach-s5p64x0/clock-s5p6450.c | |
| parent | x86: io_apic: Split setup_ioapic_ids_from_mpc() (diff) | |
| parent | x86, cacheinfo: Cleanup L3 cache index disable support (diff) | |
| download | linux-d834a9dcecae834cd6b2bc5e50e1907738d9cf6a.tar.xz linux-d834a9dcecae834cd6b2bc5e50e1907738d9cf6a.zip | |
Merge branch 'x86/amd-nb' into x86/apic-cleanups
Reason: apic cleanup series depends on x86/apic, x86/amd-nb x86/platform
Conflicts:
arch/x86/include/asm/io_apic.h
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock-s5p6450.c')
| -rw-r--r-- | arch/arm/mach-s5p64x0/clock-s5p6450.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index f9afb05b217c..7dbf3c968f53 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -80,13 +80,16 @@ static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate) __raw_writel(epll_con, S5P64X0_EPLL_CON); __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K); + printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", + clk->rate, rate); + clk->rate = rate; return 0; } static struct clk_ops s5p6450_epll_ops = { - .get_rate = s5p64x0_epll_get_rate, + .get_rate = s5p_epll_get_rate, .set_rate = s5p6450_epll_set_rate, }; @@ -186,6 +189,12 @@ static struct clk init_clocks_disable[] = { .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 3), }, { + .name = "pdma", + .id = -1, + .parent = &clk_hclk_low.clk, + .enable = s5p64x0_hclk0_ctrl, + .ctrlbit = (1 << 12), + }, { .name = "hsmmc", .id = 0, .parent = &clk_hclk_low.clk, @@ -283,12 +292,6 @@ static struct clk init_clocks[] = { .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 21), }, { - .name = "dma", - .id = -1, - .parent = &clk_hclk_low.clk, - .enable = s5p64x0_hclk0_ctrl, - .ctrlbit = (1 << 12), - }, { .name = "uart", .id = 0, .parent = &clk_pclk_low.clk, @@ -581,7 +584,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void) /* Set S5P6450 functions for clk_fout_epll */ - clk_fout_epll.enable = s5p64x0_epll_enable; + clk_fout_epll.enable = s5p_epll_enable; clk_fout_epll.ops = &s5p6450_epll_ops; clk_48m.enable = s5p64x0_clk48m_ctrl; |