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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2012-05-09 17:08:35 +0200
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2012-07-09 15:44:39 +0200
commit247c445c0fbd52c77e497ff5bfcf0dceb8afea8d (patch)
tree3334a9cd1b573fa5d447cf0876e8904d21aef105 /arch/arm/mach-s5pc100
parentARM: OMAP5: l3: Add l3 error handler support for omap5 (diff)
downloadlinux-247c445c0fbd52c77e497ff5bfcf0dceb8afea8d.tar.xz
linux-247c445c0fbd52c77e497ff5bfcf0dceb8afea8d.zip
ARM: OMAP5: Add the WakeupGen IP updates
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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