Merge branch 'master' into for-2.6.35

Conflicts:
	fs/ext3/fsync.c

Signed-off-by: Jens Axboe <jens.axboe@oracle.com>

11 files changed, 2093 insertions, 58 deletions

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 27ec167d2808..8593337784e1 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -12,12 +12,22 @@ config CPU_S5PC100
 	help
 	  Enable S5PC100 CPU support
 
+config S5PC100_SETUP_FB_24BPP
+	bool
+	help
+	  Common setup code for S5PC1XX with an 24bpp RGB display helper.
+
 config S5PC100_SETUP_SDHCI
         bool
         select S5PC1XX_SETUP_SDHCI_GPIO
         help
           Internal helper functions for S5PC100 based SDHCI systems
 
+config S5PC100_SETUP_I2C1
+	bool
+	help
+	  Common setup code for i2c bus 1.
+
 config MACH_SMDKC100
 	bool "SMDKC100"
 	select CPU_S5PC100
@@ -26,9 +36,8 @@ config MACH_SMDKC100
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
-	select S5PC1XX_SETUP_I2C0
-	select S5PC1XX_SETUP_I2C1
-	select S5PC1XX_SETUP_FB_24BPP
+	select S5PC100_SETUP_FB_24BPP
+	select S5PC100_SETUP_I2C1
 	select S5PC100_SETUP_SDHCI
 	help
 	  Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 809ff10f768f..373bc546eae8 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,10 +11,13 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)	+= cpu.o
+obj-$(CONFIG_CPU_S5PC100)	+= cpu.o gpiolib.o
+obj-$(CONFIG_CPU_S5PC100)	+= setup-i2c0.o
 
 # Helper and device support
 
+obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
+obj-$(CONFIG_S5PC100_SETUP_I2C1)	+= setup-i2c1.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
 
 # machine support
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
new file mode 100644
index 000000000000..e3fed4cfe7ad
--- /dev/null
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -0,0 +1,1358 @@
+/* linux/arch/arm/mach-s5pc100/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PC100 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+
+#include <plat/cpu-freq.h>
+#include <mach/regs-clock.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5pc100.h>
+
+static struct clk s5p_clk_otgphy = {
+	.name		= "otg_phy",
+	.id		= -1,
+};
+
+static struct clk *clk_src_mout_href_list[] = {
+	[0] = &s5p_clk_27m,
+	[1] = &clk_fin_hpll,
+};
+
+static struct clksrc_sources clk_src_mout_href = {
+	.sources	= clk_src_mout_href_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mout_href_list),
+};
+
+static struct clksrc_clk clk_mout_href = {
+	.clk = {
+		.name           = "mout_href",
+		.id             = -1,
+	},
+	.sources        = &clk_src_mout_href,
+	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
+};
+
+static struct clk *clk_src_mout_48m_list[] = {
+	[0] = &clk_xusbxti,
+	[1] = &s5p_clk_otgphy,
+};
+
+static struct clksrc_sources clk_src_mout_48m = {
+	.sources	= clk_src_mout_48m_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mout_48m_list),
+};
+
+static struct clksrc_clk clk_mout_48m = {
+	.clk = {
+		.name           = "mout_48m",
+		.id             = -1,
+	},
+	.sources        = &clk_src_mout_48m,
+	.reg_src        = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+	.clk = {
+		.name           = "mout_mpll",
+		.id             = -1,
+	},
+	.sources        = &clk_src_mpll,
+	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
+};
+
+
+static struct clksrc_clk clk_mout_apll = {
+	.clk    = {
+		.name           = "mout_apll",
+		.id             = -1,
+	},
+	.sources        = &clk_src_apll,
+	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_epll = {
+	.clk    = {
+		.name           = "mout_epll",
+		.id             = -1,
+	},
+	.sources        = &clk_src_epll,
+	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
+};
+
+static struct clk *clk_src_mout_hpll_list[] = {
+	[0] = &s5p_clk_27m,
+};
+
+static struct clksrc_sources clk_src_mout_hpll = {
+	.sources	= clk_src_mout_hpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mout_hpll_list),
+};
+
+static struct clksrc_clk clk_mout_hpll = {
+	.clk    = {
+		.name           = "mout_hpll",
+		.id             = -1,
+	},
+	.sources        = &clk_src_mout_hpll,
+	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_apll = {
+	.clk	= {
+		.name	= "div_apll",
+		.id	= -1,
+		.parent	= &clk_mout_apll.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_arm = {
+	.clk	= {
+		.name	= "div_arm",
+		.id	= -1,
+		.parent	= &clk_div_apll.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_d0_bus = {
+	.clk	= {
+		.name	= "div_d0_bus",
+		.id	= -1,
+		.parent	= &clk_div_arm.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_pclkd0 = {
+	.clk	= {
+		.name	= "div_pclkd0",
+		.id	= -1,
+		.parent	= &clk_div_d0_bus.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_secss = {
+	.clk	= {
+		.name	= "div_secss",
+		.id	= -1,
+		.parent	= &clk_div_d0_bus.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_apll2 = {
+	.clk	= {
+		.name	= "div_apll2",
+		.id	= -1,
+		.parent	= &clk_mout_apll.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
+};
+
+static struct clk *clk_src_mout_am_list[] = {
+	[0] = &clk_mout_mpll.clk,
+	[1] = &clk_div_apll2.clk,
+};
+
+struct clksrc_sources clk_src_mout_am = {
+	.sources	= clk_src_mout_am_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mout_am_list),
+};
+
+static struct clksrc_clk clk_mout_am = {
+	.clk	= {
+		.name	= "mout_am",
+		.id	= -1,
+	},
+	.sources = &clk_src_mout_am,
+	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_d1_bus = {
+	.clk	= {
+		.name	= "div_d1_bus",
+		.id	= -1,
+		.parent	= &clk_mout_am.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_mpll2 = {
+	.clk	= {
+		.name	= "div_mpll2",
+		.id	= -1,
+		.parent	= &clk_mout_am.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_mpll = {
+	.clk	= {
+		.name	= "div_mpll",
+		.id	= -1,
+		.parent	= &clk_mout_am.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
+};
+
+static struct clk *clk_src_mout_onenand_list[] = {
+	[0] = &clk_div_d0_bus.clk,
+	[1] = &clk_div_d1_bus.clk,
+};
+
+struct clksrc_sources clk_src_mout_onenand = {
+	.sources	= clk_src_mout_onenand_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mout_onenand_list),
+};
+
+static struct clksrc_clk clk_mout_onenand = {
+	.clk	= {
+		.name	= "mout_onenand",
+		.id	= -1,
+	},
+	.sources = &clk_src_mout_onenand,
+	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_onenand = {
+	.clk	= {
+		.name	= "div_onenand",
+		.id	= -1,
+		.parent	= &clk_mout_onenand.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
+};
+
+static struct clksrc_clk clk_div_pclkd1 = {
+	.clk	= {
+		.name	= "div_pclkd1",
+		.id	= -1,
+		.parent	= &clk_div_d1_bus.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_cam = {
+	.clk	= {
+		.name	= "div_cam",
+		.id	= -1,
+		.parent	= &clk_div_mpll2.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
+};
+
+static struct clksrc_clk clk_div_hdmi = {
+	.clk	= {
+		.name	= "div_hdmi",
+		.id	= -1,
+		.parent	= &clk_mout_hpll.clk,
+	},
+	.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
+};
+
+static int s5pc100_epll_enable(struct clk *clk, int enable)
+{
+	unsigned int ctrlbit = clk->ctrlbit;
+	unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
+
+	if (enable)
+		__raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
+	else
+		__raw_writel(epll_con, S5P_EPLL_CON);
+
+	return 0;
+}
+
+static unsigned long s5pc100_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static u32 epll_div[][4] = {
+	{ 32750000,	131, 3, 4 },
+	{ 32768000,	131, 3, 4 },
+	{ 36000000,	72,  3, 3 },
+	{ 45000000,	90,  3, 3 },
+	{ 45158000,	90,  3, 3 },
+	{ 45158400,	90,  3, 3 },
+	{ 48000000,	96,  3, 3 },
+	{ 49125000,	131, 4, 3 },
+	{ 49152000,	131, 4, 3 },
+	{ 60000000,	120, 3, 3 },
+	{ 67737600,	226, 5, 3 },
+	{ 67738000,	226, 5, 3 },
+	{ 73800000,	246, 5, 3 },
+	{ 73728000,	246, 5, 3 },
+	{ 72000000,	144, 3, 3 },
+	{ 84000000,	168, 3, 3 },
+	{ 96000000,	96,  3, 2 },
+	{ 144000000,	144, 3, 2 },
+	{ 192000000,	96,  3, 1 }
+};
+
+static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con;
+	unsigned int i;
+
+	if (clk->rate == rate)	/* Return if nothing changed */
+		return 0;
+
+	epll_con = __raw_readl(S5P_EPLL_CON);
+
+	epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
+				    (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
+				    (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+		return -EINVAL;
+	}
+
+	__raw_writel(epll_con, S5P_EPLL_CON);
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops s5pc100_epll_ops = {
+	.get_rate = s5pc100_epll_get_rate,
+	.set_rate = s5pc100_epll_set_rate,
+};
+
+static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
+}
+
+static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
+}
+
+static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
+}
+
+static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
+}
+
+static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
+}
+
+static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
+}
+
+static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
+}
+
+static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
+}
+
+static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
+}
+
+static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
+}
+
+static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
+}
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+	{
+		.name		= "cssys",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_0_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "secss",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_0_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "g2d",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_0_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "mdma",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_0_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "cfcon",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_0_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "nfcon",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_1_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "onenandc",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_1_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "sdm",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_2_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "seckey",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_2_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "hsmmc",
+		.id		= 2,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "hsmmc",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "hsmmc",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "modemif",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "otg",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "usbhost",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "pdma",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "pdma",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "lcd",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "rotator",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "fimc",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "fimc",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "fimc",
+		.id		= 2,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "jpeg",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "mipi-dsim",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "mipi-csis",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_1_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "g3d",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_0_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "tv",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_2_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "vp",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_2_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "mixer",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_2_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "hdmi",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_2_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "mfc",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_2_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "apc",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_3_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "iec",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_3_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "systimer",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_3_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "watchdog",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_3_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "rtc",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_3_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "i2c",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "i2c",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "spi",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "spi",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "spi",
+		.id		= 2,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "irda",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "ccan",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "ccan",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "hsitx",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "hsirx",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "iis",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "iis",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "iis",
+		.id		= 2,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "ac97",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "pcm",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "pcm",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "spdif",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "adc",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "keyif",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_5_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "spi_48m",
+		.id		= 0,
+		.parent		= &clk_mout_48m.clk,
+		.enable		= s5pc100_sclk0_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "spi_48m",
+		.id		= 1,
+		.parent		= &clk_mout_48m.clk,
+		.enable		= s5pc100_sclk0_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "spi_48m",
+		.id		= 2,
+		.parent		= &clk_mout_48m.clk,
+		.enable		= s5pc100_sclk0_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "mmc_48m",
+		.id		= 0,
+		.parent		= &clk_mout_48m.clk,
+		.enable		= s5pc100_sclk0_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "mmc_48m",
+		.id		= 1,
+		.parent		= &clk_mout_48m.clk,
+		.enable		= s5pc100_sclk0_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "mmc_48m",
+		.id		= 2,
+		.parent		= &clk_mout_48m.clk,
+		.enable		= s5pc100_sclk0_ctrl,
+		.ctrlbit	= (1 << 17),
+	},
+};
+
+static struct clk clk_vclk54m = {
+	.name		= "vclk_54m",
+	.id		= -1,
+	.rate		= 54000000,
+};
+
+static struct clk clk_i2scdclk0 = {
+	.name		= "i2s_cdclk0",
+	.id		= -1,
+};
+
+static struct clk clk_i2scdclk1 = {
+	.name		= "i2s_cdclk1",
+	.id		= -1,
+};
+
+static struct clk clk_i2scdclk2 = {
+	.name		= "i2s_cdclk2",
+	.id		= -1,
+};
+
+static struct clk clk_pcmcdclk0 = {
+	.name		= "pcm_cdclk0",
+	.id		= -1,
+};
+
+static struct clk clk_pcmcdclk1 = {
+	.name		= "pcm_cdclk1",
+	.id		= -1,
+};
+
+static struct clk *clk_src_group1_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll2.clk,
+	[2] = &clk_fin_epll,
+	[3] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group1 = {
+	.sources	= clk_src_group1_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_group1_list),
+};
+
+static struct clk *clk_src_group2_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+};
+
+struct clksrc_sources clk_src_group2 = {
+	.sources	= clk_src_group2_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_group2_list),
+};
+
+static struct clk *clk_src_group3_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+	[2] = &clk_fin_epll,
+	[3] = &clk_i2scdclk0,
+	[4] = &clk_pcmcdclk0,
+	[5] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group3 = {
+	.sources	= clk_src_group3_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_group3_list),
+};
+
+static struct clk *clk_src_group4_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+	[2] = &clk_fin_epll,
+	[3] = &clk_i2scdclk1,
+	[4] = &clk_pcmcdclk1,
+	[5] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group4 = {
+	.sources	= clk_src_group4_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_group4_list),
+};
+
+static struct clk *clk_src_group5_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+	[2] = &clk_fin_epll,
+	[3] = &clk_i2scdclk2,
+	[4] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group5 = {
+	.sources	= clk_src_group5_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_group5_list),
+};
+
+static struct clk *clk_src_group6_list[] = {
+	[0] = &s5p_clk_27m,
+	[1] = &clk_vclk54m,
+	[2] = &clk_div_hdmi.clk,
+};
+
+struct clksrc_sources clk_src_group6 = {
+	.sources	= clk_src_group6_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_group6_list),
+};
+
+static struct clk *clk_src_group7_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+	[2] = &clk_mout_hpll.clk,
+	[3] = &clk_vclk54m,
+};
+
+struct clksrc_sources clk_src_group7 = {
+	.sources	= clk_src_group7_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_group7_list),
+};
+
+static struct clk *clk_src_mmc0_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+	[2] = &clk_fin_epll,
+};
+
+struct clksrc_sources clk_src_mmc0 = {
+	.sources	= clk_src_mmc0_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mmc0_list),
+};
+
+static struct clk *clk_src_mmc12_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+	[2] = &clk_fin_epll,
+	[3] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_mmc12 = {
+	.sources	= clk_src_mmc12_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mmc12_list),
+};
+
+static struct clk *clk_src_irda_usb_list[] = {
+	[0] = &clk_mout_epll.clk,
+	[1] = &clk_div_mpll.clk,
+	[2] = &clk_fin_epll,
+	[3] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_irda_usb = {
+	.sources	= clk_src_irda_usb_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_irda_usb_list),
+};
+
+static struct clk *clk_src_pwi_list[] = {
+	[0] = &clk_fin_epll,
+	[1] = &clk_mout_epll.clk,
+	[2] = &clk_div_mpll.clk,
+};
+
+struct clksrc_sources clk_src_pwi = {
+	.sources	= clk_src_pwi_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_pwi_list),
+};
+
+static struct clksrc_clk clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "sclk_spi",
+			.id		= 0,
+			.ctrlbit	= (1 << 4),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_group1,
+		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.id		= 1,
+			.ctrlbit	= (1 << 5),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_group1,
+		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_spi",
+			.id		= 2,
+			.ctrlbit	= (1 << 6),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_group1,
+		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "uclk1",
+			.id		= -1,
+			.ctrlbit	= (1 << 3),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_group2,
+		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
+		.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_mixer",
+			.id		= -1,
+			.ctrlbit	= (1 << 6),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_group6,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
+	}, {
+		.clk	= {
+			.name		= "sclk_audio",
+			.id		= 0,
+			.ctrlbit	= (1 << 8),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_group3,
+		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
+		.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_audio",
+			.id		= 1,
+			.ctrlbit	= (1 << 9),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_group4,
+		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
+		.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_audio",
+			.id		= 2,
+			.ctrlbit	= (1 << 10),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_group5,
+		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
+		.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_lcd",
+			.id		= -1,
+			.ctrlbit	= (1 << 0),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_group7,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimc",
+			.id		= 0,
+			.ctrlbit	= (1 << 1),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_group7,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimc",
+			.id		= 1,
+			.ctrlbit	= (1 << 2),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_group7,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimc",
+			.id		= 2,
+			.ctrlbit	= (1 << 3),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_group7,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "mmc_bus",
+			.id		= 0,
+			.ctrlbit	= (1 << 12),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_mmc0,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "mmc_bus",
+			.id		= 1,
+			.ctrlbit	= (1 << 13),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_mmc12,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "mmc_bus",
+			.id		= 2,
+			.ctrlbit	= (1 << 14),
+			.enable		= s5pc100_sclk1_ctrl,
+
+		},
+		.sources = &clk_src_mmc12,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_irda",
+			.id		= 2,
+			.ctrlbit	= (1 << 10),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_irda_usb,
+		.reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_irda",
+			.id		= -1,
+			.ctrlbit	= (1 << 10),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_mmc12,
+		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_pwi",
+			.id		= -1,
+			.ctrlbit	= (1 << 1),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_pwi,
+		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
+	}, {
+		.clk	= {
+			.name		= "sclk_uhost",
+			.id		= -1,
+			.ctrlbit	= (1 << 11),
+			.enable		= s5pc100_sclk0_ctrl,
+
+		},
+		.sources = &clk_src_irda_usb,
+		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
+		.reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
+	},
+};
+
+/* Clock initialisation code */
+static struct clksrc_clk *sysclks[] = {
+	&clk_mout_apll,
+	&clk_mout_epll,
+	&clk_mout_mpll,
+	&clk_mout_hpll,
+	&clk_mout_href,
+	&clk_mout_48m,
+	&clk_div_apll,
+	&clk_div_arm,
+	&clk_div_d0_bus,
+	&clk_div_pclkd0,
+	&clk_div_secss,
+	&clk_div_apll2,
+	&clk_mout_am,
+	&clk_div_d1_bus,
+	&clk_div_mpll2,
+	&clk_div_mpll,
+	&clk_mout_onenand,
+	&clk_div_onenand,
+	&clk_div_pclkd1,
+	&clk_div_cam,
+	&clk_div_hdmi,
+};
+
+void __init_or_cpufreq s5pc100_setup_clocks(void)
+{
+	unsigned long xtal;
+	unsigned long arm;
+	unsigned long hclkd0;
+	unsigned long hclkd1;
+	unsigned long pclkd0;
+	unsigned long pclkd1;
+	unsigned long apll;
+	unsigned long mpll;
+	unsigned long epll;
+	unsigned long hpll;
+	unsigned int ptr;
+
+	/* Set S5PC100 functions for clk_fout_epll */
+	clk_fout_epll.enable = s5pc100_epll_enable;
+	clk_fout_epll.ops = &s5pc100_epll_ops;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	xtal = clk_get_rate(&clk_xtal);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
+	mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
+	epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
+	hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
+
+	printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
+			print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
+
+	clk_fout_apll.rate = apll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_mout_hpll.clk.rate = hpll;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+		s3c_set_clksrc(&clksrcs[ptr], true);
+
+	arm = clk_get_rate(&clk_div_arm.clk);
+	hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
+	pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
+	hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
+	pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
+
+	printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
+			print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
+
+	clk_f.rate = arm;
+	clk_h.rate = hclkd1;
+	clk_p.rate = pclkd1;
+}
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+	{
+		.name		= "tzic",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_0_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "intc",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_0_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "ebi",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_1_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "intmem",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_1_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "sromc",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_1_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "dmc",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_1_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "chipid",
+		.id		= -1,
+		.parent		= &clk_div_d0_bus.clk,
+		.enable		= s5pc100_d0_1_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "gpio",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_3_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "uart",
+		.id		= 0,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart",
+		.id		= 1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "uart",
+		.id		= 2,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "uart",
+		.id		= 3,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_4_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "timers",
+		.id		= -1,
+		.parent		= &clk_div_d1_bus.clk,
+		.enable		= s5pc100_d1_3_ctrl,
+		.ctrlbit	= (1 << 6),
+	},
+};
+
+static struct clk *clks[] __initdata = {
+	&clk_ext,
+	&clk_i2scdclk0,
+	&clk_i2scdclk1,
+	&clk_i2scdclk2,
+	&clk_pcmcdclk0,
+	&clk_pcmcdclk1,
+};
+
+void __init s5pc100_register_clocks(void)
+{
+	struct clk *clkp;
+	int ret;
+	int ptr;
+
+	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+		s3c_register_clksrc(sysclks[ptr], 1);
+
+	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+	clkp = init_clocks_disable;
+	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+		(clkp->enable)(clkp, 0);
+	}
+
+	s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
new file mode 100644
index 000000000000..c8e8336a3a12
--- /dev/null
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -0,0 +1,428 @@
+/*
+ * arch/arm/plat-s5pc1xx/gpiolib.c
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S5PC1XX - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+/* S5PC100 GPIO bank summary:
+ *
+ * Bank	GPIOs	Style	INT Type
+ * A0	8	4Bit	GPIO_INT0
+ * A1	5	4Bit	GPIO_INT1
+ * B	8	4Bit	GPIO_INT2
+ * C	5	4Bit	GPIO_INT3
+ * D	7	4Bit	GPIO_INT4
+ * E0	8	4Bit	GPIO_INT5
+ * E1	6	4Bit	GPIO_INT6
+ * F0	8	4Bit	GPIO_INT7
+ * F1	8	4Bit	GPIO_INT8
+ * F2	8	4Bit	GPIO_INT9
+ * F3	4	4Bit	GPIO_INT10
+ * G0	8	4Bit	GPIO_INT11
+ * G1	3	4Bit	GPIO_INT12
+ * G2	7	4Bit	GPIO_INT13
+ * G3	7	4Bit	GPIO_INT14
+ * H0	8	4Bit	WKUP_INT
+ * H1	8	4Bit	WKUP_INT
+ * H2	8	4Bit	WKUP_INT
+ * H3	8	4Bit	WKUP_INT
+ * I	8	4Bit	GPIO_INT15
+ * J0	8	4Bit	GPIO_INT16
+ * J1	5	4Bit	GPIO_INT17
+ * J2	8	4Bit	GPIO_INT18
+ * J3	8	4Bit	GPIO_INT19
+ * J4	4	4Bit	GPIO_INT20
+ * K0	8	4Bit	None
+ * K1	6	4Bit	None
+ * K2	8	4Bit	None
+ * K3	8	4Bit	None
+ * L0	8	4Bit	None
+ * L1	8	4Bit	None
+ * L2	8	4Bit	None
+ * L3	8	4Bit	None
+ */
+
+#if 0
+static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	return S3C_IRQ_GPIO(chip->base + offset);
+}
+
+static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
+{
+	int base;
+
+	base = chip->base - S5PC100_GPH0(0);
+	if (base == 0)
+		return IRQ_EINT(offset);
+	base = chip->base - S5PC100_GPH1(0);
+	if (base == 0)
+		return IRQ_EINT(8 + offset);
+	base = chip->base - S5PC100_GPH2(0);
+	if (base == 0)
+		return IRQ_EINT(16 + offset);
+	base = chip->base - S5PC100_GPH3(0);
+	if (base == 0)
+		return IRQ_EINT(24 + offset);
+	return -EINVAL;
+}
+#endif
+static struct s3c_gpio_cfg gpio_cfg = {
+	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
+	.set_pull	= s3c_gpio_setpull_updown,
+	.get_pull	= s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_eint = {
+	.cfg_eint	= 0xf,
+	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
+	.set_pull	= s3c_gpio_setpull_updown,
+	.get_pull	= s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
+	.set_pull	= s3c_gpio_setpull_updown,
+	.get_pull	= s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
+	{
+		.base	= S5PC100_GPA0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPA0(0),
+			.ngpio	= S5PC100_GPIO_A0_NR,
+			.label	= "GPA0",
+		},
+	}, {
+		.base	= S5PC100_GPA1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPA1(0),
+			.ngpio	= S5PC100_GPIO_A1_NR,
+			.label	= "GPA1",
+		},
+	}, {
+		.base	= S5PC100_GPB_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPB(0),
+			.ngpio	= S5PC100_GPIO_B_NR,
+			.label	= "GPB",
+		},
+	}, {
+		.base	= S5PC100_GPC_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPC(0),
+			.ngpio	= S5PC100_GPIO_C_NR,
+			.label	= "GPC",
+		},
+	}, {
+		.base	= S5PC100_GPD_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPD(0),
+			.ngpio	= S5PC100_GPIO_D_NR,
+			.label	= "GPD",
+		},
+	}, {
+		.base	= S5PC100_GPE0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPE0(0),
+			.ngpio	= S5PC100_GPIO_E0_NR,
+			.label	= "GPE0",
+		},
+	}, {
+		.base	= S5PC100_GPE1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPE1(0),
+			.ngpio	= S5PC100_GPIO_E1_NR,
+			.label	= "GPE1",
+		},
+	}, {
+		.base	= S5PC100_GPF0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPF0(0),
+			.ngpio	= S5PC100_GPIO_F0_NR,
+			.label	= "GPF0",
+		},
+	}, {
+		.base	= S5PC100_GPF1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPF1(0),
+			.ngpio	= S5PC100_GPIO_F1_NR,
+			.label	= "GPF1",
+		},
+	}, {
+		.base	= S5PC100_GPF2_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPF2(0),
+			.ngpio	= S5PC100_GPIO_F2_NR,
+			.label	= "GPF2",
+		},
+	}, {
+		.base	= S5PC100_GPF3_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPF3(0),
+			.ngpio	= S5PC100_GPIO_F3_NR,
+			.label	= "GPF3",
+		},
+	}, {
+		.base	= S5PC100_GPG0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPG0(0),
+			.ngpio	= S5PC100_GPIO_G0_NR,
+			.label	= "GPG0",
+		},
+	}, {
+		.base	= S5PC100_GPG1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPG1(0),
+			.ngpio	= S5PC100_GPIO_G1_NR,
+			.label	= "GPG1",
+		},
+	}, {
+		.base	= S5PC100_GPG2_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPG2(0),
+			.ngpio	= S5PC100_GPIO_G2_NR,
+			.label	= "GPG2",
+		},
+	}, {
+		.base	= S5PC100_GPG3_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPG3(0),
+			.ngpio	= S5PC100_GPIO_G3_NR,
+			.label	= "GPG3",
+		},
+	}, {
+		.base	= S5PC100_GPH0_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC100_GPH0(0),
+			.ngpio	= S5PC100_GPIO_H0_NR,
+			.label	= "GPH0",
+		},
+	}, {
+		.base	= S5PC100_GPH1_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC100_GPH1(0),
+			.ngpio	= S5PC100_GPIO_H1_NR,
+			.label	= "GPH1",
+		},
+	}, {
+		.base	= S5PC100_GPH2_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC100_GPH2(0),
+			.ngpio	= S5PC100_GPIO_H2_NR,
+			.label	= "GPH2",
+		},
+	}, {
+		.base	= S5PC100_GPH3_BASE,
+		.config	= &gpio_cfg_eint,
+		.chip	= {
+			.base	= S5PC100_GPH3(0),
+			.ngpio	= S5PC100_GPIO_H3_NR,
+			.label	= "GPH3",
+		},
+	}, {
+		.base	= S5PC100_GPI_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPI(0),
+			.ngpio	= S5PC100_GPIO_I_NR,
+			.label	= "GPI",
+		},
+	}, {
+		.base	= S5PC100_GPJ0_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPJ0(0),
+			.ngpio	= S5PC100_GPIO_J0_NR,
+			.label	= "GPJ0",
+		},
+	}, {
+		.base	= S5PC100_GPJ1_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPJ1(0),
+			.ngpio	= S5PC100_GPIO_J1_NR,
+			.label	= "GPJ1",
+		},
+	}, {
+		.base	= S5PC100_GPJ2_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPJ2(0),
+			.ngpio	= S5PC100_GPIO_J2_NR,
+			.label	= "GPJ2",
+		},
+	}, {
+		.base	= S5PC100_GPJ3_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPJ3(0),
+			.ngpio	= S5PC100_GPIO_J3_NR,
+			.label	= "GPJ3",
+		},
+	}, {
+		.base	= S5PC100_GPJ4_BASE,
+		.config	= &gpio_cfg,
+		.chip	= {
+			.base	= S5PC100_GPJ4(0),
+			.ngpio	= S5PC100_GPIO_J4_NR,
+			.label	= "GPJ4",
+		},
+	}, {
+		.base	= S5PC100_GPK0_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPK0(0),
+			.ngpio	= S5PC100_GPIO_K0_NR,
+			.label	= "GPK0",
+		},
+	}, {
+		.base	= S5PC100_GPK1_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPK1(0),
+			.ngpio	= S5PC100_GPIO_K1_NR,
+			.label	= "GPK1",
+		},
+	}, {
+		.base	= S5PC100_GPK2_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPK2(0),
+			.ngpio	= S5PC100_GPIO_K2_NR,
+			.label	= "GPK2",
+		},
+	}, {
+		.base	= S5PC100_GPK3_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPK3(0),
+			.ngpio	= S5PC100_GPIO_K3_NR,
+			.label	= "GPK3",
+		},
+	}, {
+		.base	= S5PC100_GPL0_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPL0(0),
+			.ngpio	= S5PC100_GPIO_L0_NR,
+			.label	= "GPL0",
+		},
+	}, {
+		.base	= S5PC100_GPL1_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPL1(0),
+			.ngpio	= S5PC100_GPIO_L1_NR,
+			.label	= "GPL1",
+		},
+	}, {
+		.base	= S5PC100_GPL2_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPL2(0),
+			.ngpio	= S5PC100_GPIO_L2_NR,
+			.label	= "GPL2",
+		},
+	}, {
+		.base	= S5PC100_GPL3_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPL3(0),
+			.ngpio	= S5PC100_GPIO_L3_NR,
+			.label	= "GPL3",
+		},
+	}, {
+		.base	= S5PC100_GPL4_BASE,
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PC100_GPL4(0),
+			.ngpio	= S5PC100_GPIO_L4_NR,
+			.label	= "GPL4",
+		},
+	},
+};
+
+/* FIXME move from irq-gpio.c */
+extern struct irq_chip s5pc1xx_gpioint;
+extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+
+static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
+{
+#if 0
+	/* Interrupt */
+	if (chip->config == &gpio_cfg) {
+		int i, irq;
+
+		chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
+
+		for (i = 0;  i < chip->chip.ngpio; i++) {
+			irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
+			set_irq_chip(irq, &s5pc1xx_gpioint);
+			set_irq_data(irq, &chip->chip);
+			set_irq_handler(irq, handle_level_irq);
+			set_irq_flags(irq, IRQF_VALID);
+		}
+	} else if (chip->config == &gpio_cfg_eint)
+		chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
+#endif
+}
+
+static __init int s5pc1xx_gpiolib_init(void)
+{
+	struct s3c_gpio_chip *chip;
+	int nr_chips;
+
+	chip = s5pc100_gpio_chips;
+	nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+
+	for (; nr_chips > 0; nr_chips--, chip++)
+		s5pc100_gpiolib_link(chip);
+
+	samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
+				       ARRAY_SIZE(s5pc100_gpio_chips));
+#if 0
+	/* Interrupt */
+	set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
+#endif
+	return 0;
+}
+core_initcall(s5pc1xx_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 2c4cbe8ee6b7..29a8a12d9b4f 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -12,6 +12,9 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
 #define gpio_get_value	__gpio_get_value
 #define gpio_set_value	__gpio_set_value
 #define gpio_cansleep	__gpio_cansleep
@@ -52,11 +55,6 @@
 #define S5PC100_GPIO_L2_NR	(8)
 #define S5PC100_GPIO_L3_NR	(8)
 #define S5PC100_GPIO_L4_NR	(8)
-#define S5PC100_GPIO_MP00_NR	(8)
-#define S5PC100_GPIO_MP01_NR	(8)
-#define S5PC100_GPIO_MP02_NR	(8)
-#define S5PC100_GPIO_MP03_NR	(8)
-#define S5PC100_GPIO_MP04_NR	(5)
 
 /* GPIO bank numbes */
 
@@ -65,50 +63,45 @@
  * change from one gpio bank to another can be caught.
 */
 
-#define S5PC1XX_GPIO_NEXT(__gpio) \
+#define S5PC100_GPIO_NEXT(__gpio) \
 	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
 
-enum s3c_gpio_number {
+enum s5p_gpio_number {
 	S5PC100_GPIO_A0_START	= 0,
-	S5PC100_GPIO_A1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
-	S5PC100_GPIO_B_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
-	S5PC100_GPIO_C_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
-	S5PC100_GPIO_D_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
-	S5PC100_GPIO_E0_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
-	S5PC100_GPIO_E1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
-	S5PC100_GPIO_F0_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
-	S5PC100_GPIO_F1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
-	S5PC100_GPIO_F2_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
-	S5PC100_GPIO_F3_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
-	S5PC100_GPIO_G0_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
-	S5PC100_GPIO_G1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
-	S5PC100_GPIO_G2_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
-	S5PC100_GPIO_G3_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
-	S5PC100_GPIO_H0_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
-	S5PC100_GPIO_H1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
-	S5PC100_GPIO_H2_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
-	S5PC100_GPIO_H3_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
-	S5PC100_GPIO_I_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
-	S5PC100_GPIO_J0_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
-	S5PC100_GPIO_J1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
-	S5PC100_GPIO_J2_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
-	S5PC100_GPIO_J3_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
-	S5PC100_GPIO_J4_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
-	S5PC100_GPIO_K0_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
-	S5PC100_GPIO_K1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
-	S5PC100_GPIO_K2_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
-	S5PC100_GPIO_K3_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
-	S5PC100_GPIO_L0_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
-	S5PC100_GPIO_L1_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
-	S5PC100_GPIO_L2_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
-	S5PC100_GPIO_L3_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
-	S5PC100_GPIO_L4_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
-	S5PC100_GPIO_MP00_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
-	S5PC100_GPIO_MP01_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
-	S5PC100_GPIO_MP02_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
-	S5PC100_GPIO_MP03_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
-	S5PC100_GPIO_MP04_START	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
-	S5PC100_GPIO_END	= S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
+	S5PC100_GPIO_A1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_A0),
+	S5PC100_GPIO_B_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_A1),
+	S5PC100_GPIO_C_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_B),
+	S5PC100_GPIO_D_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_C),
+	S5PC100_GPIO_E0_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_D),
+	S5PC100_GPIO_E1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_E0),
+	S5PC100_GPIO_F0_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_E1),
+	S5PC100_GPIO_F1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_F0),
+	S5PC100_GPIO_F2_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_F1),
+	S5PC100_GPIO_F3_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_F2),
+	S5PC100_GPIO_G0_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_F3),
+	S5PC100_GPIO_G1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_G0),
+	S5PC100_GPIO_G2_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_G1),
+	S5PC100_GPIO_G3_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_G2),
+	S5PC100_GPIO_H0_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_G3),
+	S5PC100_GPIO_H1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_H0),
+	S5PC100_GPIO_H2_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_H1),
+	S5PC100_GPIO_H3_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_H2),
+	S5PC100_GPIO_I_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_H3),
+	S5PC100_GPIO_J0_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_I),
+	S5PC100_GPIO_J1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_J0),
+	S5PC100_GPIO_J2_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_J1),
+	S5PC100_GPIO_J3_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_J2),
+	S5PC100_GPIO_J4_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_J3),
+	S5PC100_GPIO_K0_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_J4),
+	S5PC100_GPIO_K1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_K0),
+	S5PC100_GPIO_K2_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_K1),
+	S5PC100_GPIO_K3_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_K2),
+	S5PC100_GPIO_L0_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_K3),
+	S5PC100_GPIO_L1_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_L0),
+	S5PC100_GPIO_L2_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_L1),
+	S5PC100_GPIO_L3_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_L2),
+	S5PC100_GPIO_L4_START	= S5PC100_GPIO_NEXT(S5PC100_GPIO_L3),
+	S5PC100_GPIO_END	= S5PC100_GPIO_NEXT(S5PC100_GPIO_L4),
 };
 
 /* S5PC100 GPIO number definitions. */
@@ -146,17 +139,13 @@ enum s3c_gpio_number {
 #define S5PC100_GPL2(_nr)	(S5PC100_GPIO_L2_START + (_nr))
 #define S5PC100_GPL3(_nr)	(S5PC100_GPIO_L3_START + (_nr))
 #define S5PC100_GPL4(_nr)	(S5PC100_GPIO_L4_START + (_nr))
-#define S5PC100_MP00(_nr)	(S5PC100_GPIO_MP00_START + (_nr))
-#define S5PC100_MP01(_nr)	(S5PC100_GPIO_MP01_START + (_nr))
-#define S5PC100_MP02(_nr)	(S5PC100_GPIO_MP02_START + (_nr))
-#define S5PC100_MP03(_nr)	(S5PC100_GPIO_MP03_START + (_nr))
-#define S5PC100_MP04(_nr)	(S5PC100_GPIO_MP04_START + (_nr))
-#define S5PC100_MP05(_nr)	(S5PC100_GPIO_MP05_START + (_nr))
 
-/* It used the end of the S5PC1XX gpios */
+/* It used the end of the S5PC100 gpios */
 #define S3C_GPIO_END		S5PC100_GPIO_END
 
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS		(S5PC100_GPIO_END + 1)
 
 #include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
new file mode 100644
index 000000000000..f2283bdc941e
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -0,0 +1,71 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PC100 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)		(S3C_VA_SYS + (x))
+
+#define S5P_APLL_LOCK		S5P_CLKREG(0x00)
+#define S5P_MPLL_LOCK		S5P_CLKREG(0x04)
+#define S5P_EPLL_LOCK		S5P_CLKREG(0x08)
+#define S5P_HPLL_LOCK		S5P_CLKREG(0x0C)
+
+#define S5P_APLL_CON		S5P_CLKREG(0x100)
+#define S5P_MPLL_CON		S5P_CLKREG(0x104)
+#define S5P_EPLL_CON		S5P_CLKREG(0x108)
+#define S5P_HPLL_CON		S5P_CLKREG(0x10C)
+
+#define S5P_CLK_SRC0		S5P_CLKREG(0x200)
+#define S5P_CLK_SRC1		S5P_CLKREG(0x204)
+#define S5P_CLK_SRC2		S5P_CLKREG(0x208)
+#define S5P_CLK_SRC3		S5P_CLKREG(0x20C)
+
+#define S5P_CLK_DIV0		S5P_CLKREG(0x300)
+#define S5P_CLK_DIV1		S5P_CLKREG(0x304)
+#define S5P_CLK_DIV2		S5P_CLKREG(0x308)
+#define S5P_CLK_DIV3		S5P_CLKREG(0x30C)
+#define S5P_CLK_DIV4		S5P_CLKREG(0x310)
+
+#define S5P_CLK_OUT		S5P_CLKREG(0x400)
+
+#define S5P_CLKGATE_D00		S5P_CLKREG(0x500)
+#define S5P_CLKGATE_D01		S5P_CLKREG(0x504)
+#define S5P_CLKGATE_D02		S5P_CLKREG(0x508)
+
+#define S5P_CLKGATE_D10		S5P_CLKREG(0x520)
+#define S5P_CLKGATE_D11		S5P_CLKREG(0x524)
+#define S5P_CLKGATE_D12		S5P_CLKREG(0x528)
+#define S5P_CLKGATE_D13		S5P_CLKREG(0x52C)
+#define S5P_CLKGATE_D14		S5P_CLKREG(0x530)
+#define S5P_CLKGATE_D15		S5P_CLKREG(0x534)
+
+#define S5P_CLKGATE_D20		S5P_CLKREG(0x540)
+
+#define S5P_CLKGATE_SCLK0	S5P_CLKREG(0x560)
+#define S5P_CLKGATE_SCLK1	S5P_CLKREG(0x564)
+
+/* CLKDIV0 */
+#define S5P_CLKDIV0_D0_MASK		(0x7<<8)
+#define S5P_CLKDIV0_D0_SHIFT		(8)
+#define S5P_CLKDIV0_PCLKD0_MASK		(0x7<<12)
+#define S5P_CLKDIV0_PCLKD0_SHIFT	(12)
+
+/* CLKDIV1 */
+#define S5P_CLKDIV1_D1_MASK		(0x7<<12)
+#define S5P_CLKDIV1_D1_SHIFT		(12)
+#define S5P_CLKDIV1_PCLKD1_MASK		(0x7<<16)
+#define S5P_CLKDIV1_PCLKD1_SHIFT	(16)
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..68666913354c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - GPIO register definitions
+ */
+
+#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
+#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+
+/* S5PC100 */
+#define S5PC100_GPIO_BASE	S5PC1XX_VA_GPIO
+#define S5PC100_GPA0_BASE	(S5PC100_GPIO_BASE + 0x0000)
+#define S5PC100_GPA1_BASE	(S5PC100_GPIO_BASE + 0x0020)
+#define S5PC100_GPB_BASE	(S5PC100_GPIO_BASE + 0x0040)
+#define S5PC100_GPC_BASE	(S5PC100_GPIO_BASE + 0x0060)
+#define S5PC100_GPD_BASE	(S5PC100_GPIO_BASE + 0x0080)
+#define S5PC100_GPE0_BASE	(S5PC100_GPIO_BASE + 0x00A0)
+#define S5PC100_GPE1_BASE	(S5PC100_GPIO_BASE + 0x00C0)
+#define S5PC100_GPF0_BASE	(S5PC100_GPIO_BASE + 0x00E0)
+#define S5PC100_GPF1_BASE	(S5PC100_GPIO_BASE + 0x0100)
+#define S5PC100_GPF2_BASE	(S5PC100_GPIO_BASE + 0x0120)
+#define S5PC100_GPF3_BASE	(S5PC100_GPIO_BASE + 0x0140)
+#define S5PC100_GPG0_BASE	(S5PC100_GPIO_BASE + 0x0160)
+#define S5PC100_GPG1_BASE	(S5PC100_GPIO_BASE + 0x0180)
+#define S5PC100_GPG2_BASE	(S5PC100_GPIO_BASE + 0x01A0)
+#define S5PC100_GPG3_BASE	(S5PC100_GPIO_BASE + 0x01C0)
+#define S5PC100_GPH0_BASE	(S5PC100_GPIO_BASE + 0x0C00)
+#define S5PC100_GPH1_BASE	(S5PC100_GPIO_BASE + 0x0C20)
+#define S5PC100_GPH2_BASE	(S5PC100_GPIO_BASE + 0x0C40)
+#define S5PC100_GPH3_BASE	(S5PC100_GPIO_BASE + 0x0C60)
+#define S5PC100_GPI_BASE	(S5PC100_GPIO_BASE + 0x01E0)
+#define S5PC100_GPJ0_BASE	(S5PC100_GPIO_BASE + 0x0200)
+#define S5PC100_GPJ1_BASE	(S5PC100_GPIO_BASE + 0x0220)
+#define S5PC100_GPJ2_BASE	(S5PC100_GPIO_BASE + 0x0240)
+#define S5PC100_GPJ3_BASE	(S5PC100_GPIO_BASE + 0x0260)
+#define S5PC100_GPJ4_BASE	(S5PC100_GPIO_BASE + 0x0280)
+#define S5PC100_GPK0_BASE	(S5PC100_GPIO_BASE + 0x02A0)
+#define S5PC100_GPK1_BASE	(S5PC100_GPIO_BASE + 0x02C0)
+#define S5PC100_GPK2_BASE	(S5PC100_GPIO_BASE + 0x02E0)
+#define S5PC100_GPK3_BASE	(S5PC100_GPIO_BASE + 0x0300)
+#define S5PC100_GPL0_BASE	(S5PC100_GPIO_BASE + 0x0320)
+#define S5PC100_GPL1_BASE	(S5PC100_GPIO_BASE + 0x0340)
+#define S5PC100_GPL2_BASE	(S5PC100_GPIO_BASE + 0x0360)
+#define S5PC100_GPL3_BASE	(S5PC100_GPIO_BASE + 0x0380)
+#define S5PC100_GPL4_BASE	(S5PC100_GPIO_BASE + 0x03A0)
+#define S5PC100_EINT_BASE	(S5PC100_GPIO_BASE + 0x0E00)
+
+#define S5PC100_UHOST		(S5PC100_GPIO_BASE + 0x0B68)
+#define S5PC100_PDNEN		(S5PC100_GPIO_BASE + 0x0F80)
+
+/* PDNEN */
+#define S5PC100_PDNEN_CFG_PDNEN	(1 << 1)
+#define S5PC100_PDNEN_CFG_AUTO	(0 << 1)
+#define S5PC100_PDNEN_POWERDOWN	(1 << 0)
+#define S5PC100_PDNEN_NORMAL	(0 << 0)
+
+/* Common part */
+/* External interrupt base is same at both s5pc100 and s5pc110 */
+#define S5PC1XX_EINT_BASE	(S5PC100_EINT_BASE)
+
+#define S5PC100_GPx_INPUT(__gpio)	(0x0 << ((__gpio) * 4))
+#define S5PC100_GPx_OUTPUT(__gpio)	(0x1 << ((__gpio) * 4))
+#define S5PC100_GPx_CONMASK(__gpio)	(0xf << ((__gpio) * 4))
+
+#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
+
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index ae3c52cd0ebb..bfe67db34f04 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -35,7 +35,6 @@
 
 #include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-gpio.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
new file mode 100644
index 000000000000..6eba6cb8e2f4
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
@@ -0,0 +1,48 @@
+/*
+ * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * Base S5PC100 setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+
+#define DISR_OFFSET	0x7008
+
+void s5pc100_fb_gpio_setup_24bpp(void)
+{
+	unsigned int gpio = 0;
+
+	for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
new file mode 100644
index 000000000000..dd3174e6ecc5
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-i2c0.c
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s5pc100/setup-i2c0.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC100 I2C bus 0 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
new file mode 100644
index 000000000000..d1fec26b69ee
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-i2c1.c
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s5pc100/setup-i2c1.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *	Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC100 I2C bus 1 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
+}