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| author | Simon Guo <wei.guo.simon@gmail.com> | 2018-05-23 09:02:07 +0200 |
|---|---|---|
| committer | Paul Mackerras <paulus@ozlabs.org> | 2018-06-01 02:30:43 +0200 |
| commit | 7284ca8a5eaee311d2e4aec73b2df9bd57e0cdcb (patch) | |
| tree | 9425521c48ed9b4b5f073e0ba964262451f1da93 /arch/arm/mach-sa1100/h3xxx.c | |
| parent | KVM: PPC: Book3S PR: Add guard code to prevent returning to guest with PR=0 a... (diff) | |
| download | linux-7284ca8a5eaee311d2e4aec73b2df9bd57e0cdcb.tar.xz linux-7284ca8a5eaee311d2e4aec73b2df9bd57e0cdcb.zip | |
KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM
Currently guest kernel doesn't handle TAR facility unavailable and it
always runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not
a frequent-use register and it is not included in SVCPU struct.
Due to the above, the checkpointed TAR val might be a bogus TAR val.
To solve this issue, we will make vcpu->arch.fscr tar bit consistent
with shadow_fscr when TM is enabled.
At the end of emulating treclaim., the correct TAR val need to be loaded
into the register if FSCR_TAR bit is on.
At the beginning of emulating trechkpt., TAR needs to be flushed so that
the right tar val can be copied into tar_tm.
Tested with:
tools/testing/selftests/powerpc/tm/tm-tar
tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar (remove DSCR/PPR
related testing).
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Diffstat (limited to 'arch/arm/mach-sa1100/h3xxx.c')
0 files changed, 0 insertions, 0 deletions