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author | Evgeniy Dushistov <dushistov@mail.ru> | 2014-07-26 17:56:59 +0200 |
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committer | Jason Cooper <jason@lakedaemon.net> | 2014-11-01 23:07:45 +0100 |
commit | 9ece8839b1277fb9128ff6833411614ab6c88d68 (patch) | |
tree | b2565d5c213db0f7dc6447909a8a48a0347d39f0 /arch/arm/mach-socfpga/platsmp.c | |
parent | ARM: mvebu: armada xp: Generalize use of i2c quirk (diff) | |
download | linux-9ece8839b1277fb9128ff6833411614ab6c88d68.tar.xz linux-9ece8839b1277fb9128ff6833411614ab6c88d68.zip |
ARM: orion: Fix for certain sequence of request_irq can cause irq storm
The problem is that hardware handled by arm/plat-orion/gpio.c,
require ack for edge irq, and no ack for level irq.
The code handle this issue, by two "struct irq_chip_type" per
one "struct irq_chip_generic". For one "struct irq_chip_generic"
irq_ack pointer is setted, for another it is NULL.
But we have only one mask_cache per two "struct irq_chip_type".
So if we
1)unmask interrupt A for "edge type" trigger,
2)unmask interrupt B for "level type" trigger,
3)unmask interrupt C for "edge type",
we, because of usage of generic irq_gc_mask_clr_bit/irq_gc_mask_set_bit,
have hardware configured to trigger interrupt B on "edge type",
because of shared mask_cache. But kernel think that B is "level type",
so when interrupt B occur via "edge" reason, we don't ack it,
and B triggered again and again.
Signed-off-by: Evgeniy A. Dushistov <dushistov@mail.ru>
Link: https://lkml.kernel.org/r/20140726155659.GA22977@fifteen
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-socfpga/platsmp.c')
0 files changed, 0 insertions, 0 deletions