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authorStephen Warren <swarren@nvidia.com>2012-02-02 20:24:19 +0100
committerOlof Johansson <olof@lixom.net>2012-03-04 19:47:30 +0100
commit8c690fdf465be9d97229f6bb0e6346624d6753a9 (patch)
tree0c061609e566ed4aa704b99c71a45b26939c21c2 /arch/arm/mach-tegra/board-dt-tegra30.c
parentARM: tegra: support for secondary cores on Tegra30 (diff)
downloadlinux-8c690fdf465be9d97229f6bb0e6346624d6753a9.tar.xz
linux-8c690fdf465be9d97229f6bb0e6346624d6753a9.zip
ARM: dt: Explicitly configure all serial ports on Tegra Cardhu
The ports are used as follows: UART1/A: Routed to debug dongle UART2/B: GPS UART3/C: Bluetooth UART4/D: Routed to debug dongle UART5/E: Not connected The debug dongle has jumpers to connect either UART1/A or UART4/D to the DB-9 connector. UART1/A is typically used on Cardhu, and is the option we assume here. For now, only enable UART1/A, and explicitly disable all other ports. The explicit disable prevents the message "of_serial 70006040.serial: no clock-frequency property set" being printed during boot. Enabling the other ports requires their clocks to be enabled, or accesses to the registers will hang. At present, this requires adding entries into board-dt-tegra30.c's tegra_dt_clk_init_table[]. Lets punt on that and wait for the common clock bindings to set this all up, although that will also requiring adding clock support to 8250.c. While we're at it, fix board-dt-tegra30.c to enable the correct clock for the debug UART. We got away with this before, because the bootloader already enabled it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/board-dt-tegra30.c')
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index b4124b12a779..11f7abd775b3 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -56,7 +56,7 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
/* name parent rate enabled */
- { "uartd", "pll_p", 408000000, true },
+ { "uarta", "pll_p", 408000000, true },
{ NULL, NULL, 0, 0},
};