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authorStephen Warren <swarren@nvidia.com>2012-04-21 00:58:18 +0200
committerStephen Warren <swarren@nvidia.com>2012-04-25 23:22:09 +0200
commit7ff4db0967bd7d617c77dc5a66c0d95166277817 (patch)
tree43328bab20e3fe0e2c0a613b5860eabd4802342f /arch/arm/mach-tegra/common.c
parentARM: tegra: reparent sclk to pll_c_out1 (diff)
downloadlinux-7ff4db0967bd7d617c77dc5a66c0d95166277817.tar.xz
linux-7ff4db0967bd7d617c77dc5a66c0d95166277817.zip
ARM: tegra: fix pclk rate
Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the rate of hclk. Since pclk is derived from that, and only has integer dividers, the pclk rate needs to change in the same fashion, from 54MHz to 60MHz. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r--arch/arm/mach-tegra/common.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index e96900418682..a4fba8835136 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -87,7 +87,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
{ "pll_c_out1", "pll_c", 120000000, true },
{ "sclk", "pll_c_out1", 120000000, true },
{ "hclk", "sclk", 120000000, true },
- { "pclk", "hclk", 54000000, true },
+ { "pclk", "hclk", 60000000, true },
{ "csite", NULL, 0, true },
{ "emc", NULL, 0, true },
{ "cpu", NULL, 0, true },