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authorJoseph Lo <josephl@nvidia.com>2013-10-11 11:58:38 +0200
committerStephen Warren <swarren@nvidia.com>2013-10-19 00:28:10 +0200
commitf0c4ac1329452e5d31a03b4bb711c330065c0369 (patch)
tree38f618cae4e1cf374681d6569aeb486dec44aa69 /arch/arm/mach-tegra/pm.c
parentARM: tegra: re-calculate the LP1 data for Tegra30/114 (diff)
downloadlinux-f0c4ac1329452e5d31a03b4bb711c330065c0369.tar.xz
linux-f0c4ac1329452e5d31a03b4bb711c330065c0369.zip
ARM: tegra: add LP1 support code for Tegra124
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just need to update the difference of the register address, then we can continue to share the code. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
-rw-r--r--arch/arm/mach-tegra/pm.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 36ed88af1cc1..4ae0286b468d 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
break;
case TEGRA30:
case TEGRA114:
+ case TEGRA124:
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
- IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+ IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+ IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
tegra_tear_down_cpu = tegra30_tear_down_cpu;
break;
}
@@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
break;
case TEGRA30:
case TEGRA114:
+ case TEGRA124:
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
- IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+ IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+ IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
tegra30_lp1_iram_hook();
break;
default:
@@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void)
break;
case TEGRA30:
case TEGRA114:
+ case TEGRA124:
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
- IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+ IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+ IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
tegra30_sleep_core_init();
break;
default: