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| author | Dmitry Osipenko <digetx@gmail.com> | 2018-11-24 22:13:47 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-01-16 13:21:57 +0100 |
| commit | d8f584099271ce51b59a4c5cec0c0f72e638145e (patch) | |
| tree | fb2f6a78fb3c067169b9acfe6075ed0999d6edd3 /arch/arm/mach-tegra/sleep-tegra20.S | |
| parent | ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+ (diff) | |
| download | linux-d8f584099271ce51b59a4c5cec0c0f72e638145e.tar.xz linux-d8f584099271ce51b59a4c5cec0c0f72e638145e.zip | |
ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30
The DRAM refresh-interval is getting erroneously set to "1" on exiting
from memory self-refreshing mode. The clobbered interval causes the
"refresh request overflow timeout" error raised by the External Memory
Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20,
but EMC registers are not latched after exiting from self-refreshing mode
on Tegra20 and hence refresh-interval is not altered until an event that
causes registers latching happens.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-tegra20.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-tegra20.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 5c8e638ee51a..dedeebfccc55 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -32,7 +32,6 @@ #define EMC_CFG 0xc #define EMC_ADR_CFG 0x10 -#define EMC_REFRESH 0x70 #define EMC_NOP 0xdc #define EMC_SELF_REF 0xe0 #define EMC_REQ_CTRL 0x2b0 @@ -397,7 +396,6 @@ padload_done: mov r1, #1 str r1, [r0, #EMC_NOP] str r1, [r0, #EMC_NOP] - str r1, [r0, #EMC_REFRESH] emc_device_mask r1, r0 |