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| author | Joseph Lo <josephl@nvidia.com> | 2013-07-03 11:50:38 +0200 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-07-19 18:08:05 +0200 |
| commit | ac2527bfc21739b77d687df1bfc4e973103fef7b (patch) | |
| tree | e217d872db97681d551caf07f38129a8f3fa473f /arch/arm/mach-tegra/sleep.S | |
| parent | ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9 (diff) | |
| download | linux-ac2527bfc21739b77d687df1bfc4e973103fef7b.tar.xz linux-ac2527bfc21739b77d687df1bfc4e973103fef7b.zip | |
ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL
Adding a flag for tegra_disable_clean_inv_dcache to flush cache as LoUIS
or ALL. After this patch, the v7_flush_dcache_louis is used for CPU hotplug
and CPU suspend in CPU power down (e.g. CPU idle power-down mode) case. And
the v7_flush_dcache_all is used for CPU cluster power down (e.g. suspend to
LP2 mode).
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 9daaef26b0f6..6d6600dcbfe2 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -56,7 +56,9 @@ ENTRY(tegra_disable_clean_inv_dcache) isb /* Flush the D-cache */ - bl v7_flush_dcache_louis + cmp r0, #TEGRA_FLUSH_CACHE_ALL + blne v7_flush_dcache_louis + bleq v7_flush_dcache_all /* Trun off coherency */ exit_smp r4, r5 @@ -73,9 +75,12 @@ ENDPROC(tegra_disable_clean_inv_dcache) * tegra?_tear_down_cpu */ ENTRY(tegra_sleep_cpu_finish) + mov r4, r0 /* Flush and disable the L1 data cache */ + mov r0, #TEGRA_FLUSH_CACHE_ALL bl tegra_disable_clean_inv_dcache + mov r0, r4 mov32 r6, tegra_tear_down_cpu ldr r1, [r6] add r1, r1, r0 |