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authorStephen Warren <swarren@nvidia.com>2012-04-25 20:10:19 +0200
committerStephen Warren <swarren@nvidia.com>2012-04-25 23:23:14 +0200
commitaea812e1ac80a491d39396e2a2d15bb725933c84 (patch)
treee31f1c047e43a10d410b3b11471530627c98aaf5 /arch/arm/mach-tegra/tegra2_clocks.c
parentLinux 3.4-rc2 (diff)
downloadlinux-aea812e1ac80a491d39396e2a2d15bb725933c84.tar.xz
linux-aea812e1ac80a491d39396e2a2d15bb725933c84.zip
ARM: tegra: add pll_x freq table entry for 750MHz
Some SKUs limit the maximum CPU frequency to 750MHz; see tegra2_pllx_clk_init(). The pll_x frequency table needs an entry for this frequency, or there will be continual log spam from the cpufreq driver attempting to set this rate, yet there being no table entry for it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 592a4eeb5328..2cae5cbc20ba 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1764,6 +1764,12 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
{ 19200000, 760000000, 950, 24, 1, 8},
{ 26000000, 760000000, 760, 26, 1, 12},
+ /* 750 MHz */
+ { 12000000, 750000000, 750, 12, 1, 12},
+ { 13000000, 750000000, 750, 13, 1, 12},
+ { 19200000, 750000000, 625, 16, 1, 8},
+ { 26000000, 750000000, 750, 26, 1, 12},
+
/* 608 MHz */
{ 12000000, 608000000, 608, 12, 1, 12},
{ 13000000, 608000000, 608, 13, 1, 12},