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authorJonas Aaberg <jonas.aberg@stericsson.com>2011-09-14 09:10:54 +0200
committerLinus Walleij <linus.walleij@linaro.org>2011-09-22 15:43:26 +0200
commit5f5663a436a4c54ede441b4f8ab3f947e78db345 (patch)
tree1b737e2136237172751e9d6e86fd5de6961b1d2e /arch/arm/mach-ux500/timer.c
parentARM: ux500: add support for clocksource DBX500 PRCMU (diff)
downloadlinux-5f5663a436a4c54ede441b4f8ab3f947e78db345.tar.xz
linux-5f5663a436a4c54ede441b4f8ab3f947e78db345.zip
ARM: ux500: Move timer code to separate file
Just split off the timer code to its own file so we have a more fine-grained file tree. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ux500/timer.c')
-rw-r--r--arch/arm/mach-ux500/timer.c58
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
new file mode 100644
index 000000000000..36a82bf57d55
--- /dev/null
+++ b/arch/arm/mach-ux500/timer.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
+ */
+#include <linux/io.h>
+#include <linux/clksrc-dbx500-prcmu.h>
+
+#include <asm/localtimer.h>
+
+#include <plat/mtu.h>
+
+#include <mach/setup.h>
+#include <mach/hardware.h>
+
+static void __init ux500_timer_init(void)
+{
+ if (cpu_is_u5500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = __io_address(U5500_TWD_BASE);
+#endif
+ mtu_base = __io_address(U5500_MTU0_BASE);
+ clksrc_dbx500_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
+ } else if (cpu_is_u8500()) {
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = __io_address(U8500_TWD_BASE);
+#endif
+ mtu_base = __io_address(U8500_MTU0_BASE);
+ clksrc_dbx500_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
+ } else {
+ ux500_unknown_soc();
+ }
+
+ /*
+ * Here we register the timerblocks active in the system.
+ * Localtimers (twd) is started when both cpu is up and running.
+ * MTU register a clocksource, clockevent and sched_clock.
+ * Since the MTU is located in the VAPE power domain
+ * it will be cleared in sleep which makes it unsuitable.
+ * We however need it as a timer tick (clockevent)
+ * during boot to calibrate delay until twd is started.
+ * RTC-RTT have problems as timer tick during boot since it is
+ * depending on delay which is not yet calibrated. RTC-RTT is in the
+ * always-on powerdomain and is used as clockevent instead of twd when
+ * sleeping.
+ * The PRCMU timer 4(3 for DB5500) register a clocksource and
+ * sched_clock with higher rating then MTU since is always-on.
+ *
+ */
+
+ nmdk_timer_init();
+ clksrc_dbx500_prcmu_init();
+}
+
+struct sys_timer ux500_timer = {
+ .init = ux500_timer_init,
+};