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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-06-24 20:43:15 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-07-18 13:29:02 +0200 |
| commit | af040ffc9ba1e079ee4c0748aff64fa3d4716fa5 (patch) | |
| tree | 03d58af8c3d16a777ee93e35d9f7aef15293a163 /arch/arm/mach-vexpress | |
| parent | ARM: 8099/1: EXYNOS: Fix MCPM build with SUSPEND=n (diff) | |
| download | linux-af040ffc9ba1e079ee4c0748aff64fa3d4716fa5.tar.xz linux-af040ffc9ba1e079ee4c0748aff64fa3d4716fa5.zip | |
ARM: make it easier to check the CPU part number correctly
Ensure that platform maintainers check the CPU part number in the right
manner: the CPU part number is meaningless without also checking the
CPU implement(e|o)r (choose your preferred spelling!) Provide an
interface which returns both the implementer and part number together,
and update the definitions to include the implementer.
Mark the old function as being deprecated... indeed, using the old
function with the definitions will now always evaluate as false, so
people must update their un-merged code to the new function. While
this could be avoided by adding new definitions, we'd also have to
create new names for them which would be awkward.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-vexpress')
| -rw-r--r-- | arch/arm/mach-vexpress/tc2_pm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c index 54a9fff77c7d..2fb78b4648cb 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-vexpress/tc2_pm.c @@ -152,7 +152,7 @@ static void tc2_pm_down(u64 residency) if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { arch_spin_unlock(&tc2_pm_lock); - if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) { + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { /* * On the Cortex-A15 we need to disable * L2 prefetching before flushing the cache. @@ -326,7 +326,7 @@ static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) static void __init tc2_cache_off(void) { pr_info("TC2: disabling cache during MCPM loopback test\n"); - if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) { + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { /* disable L2 prefetching on the Cortex-A15 */ asm volatile( "mcr p15, 1, %0, c15, c0, 3 \n\t" |