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author | Arnd Bergmann <arnd@arndb.de> | 2014-09-25 17:42:57 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2014-09-25 17:42:57 +0200 |
commit | e36087998a3b01f3c6c93fa9465e40103f427315 (patch) | |
tree | 029c1db87eb84dc72e796174455f0c453885fa74 /arch/arm/mach-zynq/platsmp.c | |
parent | ARM: meson: add basic support for MesonX SoCs (diff) | |
parent | ARM: zynq: Remove useless L2C AUX setting (diff) | |
download | linux-e36087998a3b01f3c6c93fa9465e40103f427315.tar.xz linux-e36087998a3b01f3c6c93fa9465e40103f427315.zip |
Merge tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx into next/soc
Pull "arm: Xilinx Zynq cleanup patches for v3.18" from Michal Simek:
- PM support
- Fix L2 useless setting
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Remove useless L2C AUX setting
ARM: zynq: Rename 'zynq_platform_cpu_die'
ARM: zynq: Remove hotplug.c
ARM: zynq: Synchronise zynq_cpu_die/kill
ARM: zynq: cpuidle: Remove pointless code
ARM: zynq: Remove invalidate cache for cpu die
ARM: zynq: PM: Enable DDR clock stop
ARM: zynq: DT: Add DDRC node
Documentation: devicetree: Add binding for Synopsys DDR controller
ARM: zynq: PM: Enable A9 internal clock gating feature
Diffstat (limited to 'arch/arm/mach-zynq/platsmp.c')
-rw-r--r-- | arch/arm/mach-zynq/platsmp.c | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index abc82ef085c1..52d768ff7857 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -112,20 +112,59 @@ static void __init zynq_smp_prepare_cpus(unsigned int max_cpus) scu_enable(zynq_scu_base); } +/** + * zynq_secondary_init - Initialize secondary CPU cores + * @cpu: CPU that is initialized + * + * This function is in the hotplug path. Don't move it into the + * init section!! + */ +static void zynq_secondary_init(unsigned int cpu) +{ + zynq_core_pm_init(); +} + #ifdef CONFIG_HOTPLUG_CPU static int zynq_cpu_kill(unsigned cpu) { + unsigned long timeout = jiffies + msecs_to_jiffies(50); + + while (zynq_slcr_cpu_state_read(cpu)) + if (time_after(jiffies, timeout)) + return 0; + zynq_slcr_cpu_stop(cpu); return 1; } + +/** + * zynq_cpu_die - Let a CPU core die + * @cpu: Dying CPU + * + * Platform-specific code to shutdown a CPU. + * Called with IRQs disabled on the dying CPU. + */ +static void zynq_cpu_die(unsigned int cpu) +{ + zynq_slcr_cpu_state_write(cpu, true); + + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) + cpu_do_idle(); +} #endif struct smp_operations zynq_smp_ops __initdata = { .smp_init_cpus = zynq_smp_init_cpus, .smp_prepare_cpus = zynq_smp_prepare_cpus, .smp_boot_secondary = zynq_boot_secondary, + .smp_secondary_init = zynq_secondary_init, #ifdef CONFIG_HOTPLUG_CPU - .cpu_die = zynq_platform_cpu_die, + .cpu_die = zynq_cpu_die, .cpu_kill = zynq_cpu_kill, #endif }; |