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| author | Michal Simek <michal.simek@xilinx.com> | 2013-07-31 09:19:59 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-05-20 16:13:48 +0200 |
| commit | 00f7dc636366f72474b1896f4990b3c086cd2c6d (patch) | |
| tree | 34e49e11098aa4f38d220f583d2e3028804348cd /arch/arm/mach-zynq/slcr.c | |
| parent | Linux 3.15-rc1 (diff) | |
| download | linux-00f7dc636366f72474b1896f4990b3c086cd2c6d.tar.xz linux-00f7dc636366f72474b1896f4990b3c086cd2c6d.zip | |
ARM: zynq: Add support for SOC_BUS
Provide information through SOC_BUS to user space.
Silicon revision is provided through devcfg device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynq/slcr.c')
| -rw-r--r-- | arch/arm/mach-zynq/slcr.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index a37d49a6e657..c43a2d16e223 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -26,10 +26,13 @@ #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ +#define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */ #define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_A9_CPU_CLKSTOP 0x10 #define SLCR_A9_CPU_RST 0x1 +#define SLCR_PSS_IDCODE_DEVICE_SHIFT 12 +#define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F static void __iomem *zynq_slcr_base; static struct regmap *zynq_slcr_regmap; @@ -83,6 +86,22 @@ static inline int zynq_slcr_unlock(void) } /** + * zynq_slcr_get_device_id - Read device code id + * + * Return: Device code id + */ +u32 zynq_slcr_get_device_id(void) +{ + u32 val; + + zynq_slcr_read(&val, SLCR_PSS_IDCODE); + val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT; + val &= SLCR_PSS_IDCODE_DEVICE_MASK; + + return val; +} + +/** * zynq_slcr_system_reset - Reset the entire system. */ void zynq_slcr_system_reset(void) |