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authorTony Lindgren <tony@atomide.com>2016-03-30 19:36:06 +0200
committerTony Lindgren <tony@atomide.com>2016-03-30 19:36:06 +0200
commit1809de7e7d37c585e01a1bcc583ea92b78fc759d (patch)
tree76c5b35c2b04eafce86a1a729c02ab705eba44bc /arch/arm/mach-zynq/slcr.c
parentARM: OMAP2+: Use srst_udelay for USB on dm814x (diff)
parentARM: OMAP2+: hwmod: Fix updating of sysconfig register (diff)
downloadlinux-1809de7e7d37c585e01a1bcc583ea92b78fc759d.tar.xz
linux-1809de7e7d37c585e01a1bcc583ea92b78fc759d.zip
Merge tag 'for-v4.6-rc/omap-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.6/fixes
ARM: OMAP2+: first hwmod fix for v4.6-rc Fix a longstanding bug in the hwmod code that could cause hardware SYSCONFIG register values to not match the kernel's idea of what they should be, and that could result in lower performance during IP block idle entry. Basic build, boot, and PM test logs are available here: http://www.pwsan.com/omap/testlogs/omap-hwmod-fixes-a-for-v4.6-rc/20160326231727/
Diffstat (limited to 'arch/arm/mach-zynq/slcr.c')
-rw-r--r--arch/arm/mach-zynq/slcr.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 26320ebf3493..f0292a30e6f6 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -28,6 +28,7 @@
#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
#define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
+#define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */
#define SLCR_UNLOCK_MAGIC 0xDF0D
#define SLCR_A9_CPU_CLKSTOP 0x10
@@ -227,6 +228,9 @@ int __init zynq_early_slcr_init(void)
/* unlock the SLCR so that registers can be changed */
zynq_slcr_unlock();
+ /* See AR#54190 design advisory */
+ regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202);
+
register_restart_handler(&zynq_slcr_restart_nb);
pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);