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authorRussell King <rmk+kernel@arm.linux.org.uk>2015-04-03 12:10:46 +0200
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-04-14 23:26:51 +0200
commit5aca370826a2487aaaae5db31f6bb0b906e9755f (patch)
tree345f23517edaff16eaeb7620bbf9030c83a16f20 /arch/arm/mm/cache-v7.S
parentARM: allow 16-bit instructions in ALT_UP() (diff)
downloadlinux-5aca370826a2487aaaae5db31f6bb0b906e9755f.tar.xz
linux-5aca370826a2487aaaae5db31f6bb0b906e9755f.zip
ARM: cache-v7: use movw/movt instructions
We always build cache-v7.S for ARMv7, so we can use the ARMv7 16-bit move instructions to load large constants, rather than using constants in a literal pool. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r--arch/arm/mm/cache-v7.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index b966656d2c2d..30c81e7d6aaa 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -36,10 +36,10 @@ ENTRY(v7_invalidate_l1)
mcr p15, 2, r0, c0, c0, 0
mrc p15, 1, r0, c0, c0, 0
- ldr r1, =0x7fff
+ movw r1, #0x7fff
and r2, r1, r0, lsr #13
- ldr r1, =0x3ff
+ movw r1, #0x3ff
and r3, r1, r0, lsr #3 @ NumWays - 1
add r2, r2, #1 @ NumSets
@@ -95,7 +95,8 @@ ENTRY(v7_flush_dcache_louis)
#ifdef CONFIG_ARM_ERRATA_643719
ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register
ALT_UP(reteq lr) @ LoUU is zero, so nothing to do
- ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p?
+ movweq r1, #:lower16:0x410fc090 @ ID of ARM Cortex A9 r0p?
+ movteq r1, #:upper16:0x410fc090
biceq r2, r2, #0x0000000f @ clear minor revision number
teqeq r2, r1 @ test for errata affected core and if so...
orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne')
@@ -140,10 +141,10 @@ flush_levels:
#endif
and r2, r1, #7 @ extract the length of the cache lines
add r2, r2, #4 @ add 4 (line length offset)
- ldr r4, =0x3ff
+ movw r4, #0x3ff
ands r4, r4, r1, lsr #3 @ find maximum number on the way size
clz r5, r4 @ find bit position of way size increment
- ldr r7, =0x7fff
+ movw r7, #0x7fff
ands r7, r7, r1, lsr #13 @ extract max number of the index size
loop1:
mov r9, r7 @ create working copy of max index