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authorWill Deacon <will.deacon@arm.com>2013-05-13 13:01:12 +0200
committerWill Deacon <will.deacon@arm.com>2013-08-12 13:25:45 +0200
commit6abdd491698a27f7df04a32ca12cc453810e4396 (patch)
tree34f4aa721441439634e721fe0eeba614b076a889 /arch/arm/mm/cache-v7.S
parentARM: tlb: reduce scope of barrier domains for TLB invalidation (diff)
downloadlinux-6abdd491698a27f7df04a32ca12cc453810e4396.tar.xz
linux-6abdd491698a27f7df04a32ca12cc453810e4396.zip
ARM: mm: use inner-shareable barriers for TLB and user cache operations
System-wide barriers aren't required for situations where we only need to make visibility and ordering guarantees in the inner-shareable domain (i.e. we are not dealing with devices or potentially incoherent CPUs). This patch changes the v7 TLB operations, coherent_user_range and dcache_clean_area functions to user inner-shareable barriers. For cache maintenance, only the store access type is required to ensure completion. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r--arch/arm/mm/cache-v7.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 515b00064da8..b5c467a65c27 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -282,7 +282,7 @@ ENTRY(v7_coherent_user_range)
add r12, r12, r2
cmp r12, r1
blo 1b
- dsb
+ dsb ishst
icache_line_size r2, r3
sub r3, r2, #1
bic r12, r0, r3
@@ -294,7 +294,7 @@ ENTRY(v7_coherent_user_range)
mov r0, #0
ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
- dsb
+ dsb ishst
isb
mov pc, lr