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authorRussell King <rmk+kernel@arm.linux.org.uk>2015-04-03 12:21:42 +0200
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-04-14 23:26:52 +0200
commitcd8b24d9e852b53e68c69a086358c81423dfb8d1 (patch)
tree9393ff2f7d6bd650f802ff5408b5facdc3b5bc86 /arch/arm/mm/cache-v7.S
parentARM: cache-v7: shift CLIDR to extract appropriate field before masking (diff)
downloadlinux-cd8b24d9e852b53e68c69a086358c81423dfb8d1.tar.xz
linux-cd8b24d9e852b53e68c69a086358c81423dfb8d1.zip
ARM: cache-v7: consolidate initialisation of cache level index
Both v7_flush_cache_louis and v7_flush_dcache_all both begin the flush_levels loop with r10 initialised to zero. In each case, this is done immediately prior to entering the loop. Branch to this instruction in v7_flush_dcache_all from v7_flush_cache_louis and eliminate the unnecessary initialisation in v7_flush_cache_louis. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r--arch/arm/mm/cache-v7.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index d062f8cbb886..5b5d0c00bca7 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -103,8 +103,7 @@ ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position
moveqs r3, #1 << 1 @ fix LoUIS value (and set flags state to 'ne')
#endif
reteq lr @ return if level == 0
- mov r10, #0 @ r10 (starting level) = 0
- b flush_levels @ start flushing cache levels
+ b start_flush_levels @ start flushing cache levels
ENDPROC(v7_flush_dcache_louis)
/*
@@ -122,6 +121,7 @@ ENTRY(v7_flush_dcache_all)
mov r3, r0, lsr #23 @ move LoC into position
ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
beq finished @ if loc is 0, then no need to clean
+start_flush_levels:
mov r10, #0 @ start clean at cache level 0
flush_levels:
add r2, r10, r10, lsr #1 @ work out 3x current cache level