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| author | Matt Fleming <matt@console-pimps.org> | 2009-12-13 15:38:50 +0100 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-12-17 06:31:20 +0100 |
| commit | 5d9b4b19f118abfb75e352841f7bf74580d7e427 (patch) | |
| tree | 5b9d0ec51bd12165d842d1d8a208e7568971757b /arch/arm/mm/flush.c | |
| parent | sh: Abstract the number of page table levels (diff) | |
| download | linux-5d9b4b19f118abfb75e352841f7bf74580d7e427.tar.xz linux-5d9b4b19f118abfb75e352841f7bf74580d7e427.zip | |
sh: Definitions for 3-level page table layout
If using 64-bit PTEs and 4K pages then each page table has 512 entries
(as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows
the convention that all structures in the page table (pgd_t, pmd_t,
pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require
64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs
it is only possible to map 1GB of virtual address space.
In order to map all 4GB of virtual address space we need to adopt a
3-level page table layout. This actually works out better for
CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2
areas (which are untranslated) instead of 256.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/arm/mm/flush.c')
0 files changed, 0 insertions, 0 deletions