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authorCyril Chemparathy <cyril@ti.com>2012-07-21 21:55:04 +0200
committerWill Deacon <will.deacon@arm.com>2013-05-30 17:02:15 +0200
commit4756dcbfd37819a8359d3c69a22be2ee41666d0f (patch)
treea9c172f6940e607b9c0c9a3bd7393bf0cc03e940 /arch/arm/mm/highmem.c
parentARM: LPAE: factor out T1SZ and TTBR1 computations (diff)
downloadlinux-4756dcbfd37819a8359d3c69a22be2ee41666d0f.tar.xz
linux-4756dcbfd37819a8359d3c69a22be2ee41666d0f.zip
ARM: LPAE: accomodate >32-bit addresses for page table base
This patch redefines the early boot time use of the R4 register to steal a few low order bits (ARCH_PGD_SHIFT bits) on LPAE systems. This allows for up to 38-bit physical addresses. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Subash Patel <subash.rp@samsung.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm/highmem.c')
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