diff options
| author | Will Deacon <will.deacon@arm.com> | 2014-05-09 19:36:27 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-26 00:47:46 +0200 |
| commit | 9581960a40ab0e281b695bf03744c8924ec3b5d0 (patch) | |
| tree | ff48508723eef430b3afb1fe48f19945acb3ed00 /arch/arm/mm/mmu.c | |
| parent | ARM: 8046/1: proc: add support for the Cortex-A17 processor (diff) | |
| download | linux-9581960a40ab0e281b695bf03744c8924ec3b5d0.tar.xz linux-9581960a40ab0e281b695bf03744c8924ec3b5d0.zip | |
ARM: 8055/1: cacheflush: use -st dsb option for ensuring completion
dsb st can be used to ensure completion of pending cache maintenance
operations, so use it for the v7 cache maintenance operations.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm/mm/mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 09c0a16165dc..a991ce2f18d4 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -1465,7 +1465,7 @@ void __init early_paging_init(const struct machine_desc *mdesc, * just complicate the code. */ flush_cache_louis(); - dsb(); + dsb(ishst); isb(); /* remap level 1 table */ |