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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-04-09 16:00:11 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-04-09 16:00:11 +0200 |
| commit | 85b3cce880a19e78286570d5fd004cc3cac06f57 (patch) | |
| tree | bf251707e89682972089dfec185ca5625db88e34 /arch/arm/mm/mmu.c | |
| parent | ARM: 6043/1: AT91 slow-clock resume: Don't wait for a disabled PLL to lock (diff) | |
| download | linux-85b3cce880a19e78286570d5fd004cc3cac06f57.tar.xz linux-85b3cce880a19e78286570d5fd004cc3cac06f57.zip | |
ARM: Fix ioremap_cached()/ioremap_wc() for SMP platforms
Write combining/cached device mappings are not setting the shared bit,
which could potentially cause problems on SMP systems since the cache
lines won't participate in the cache coherency protocol.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mm/mmu.c')
| -rw-r--r-- | arch/arm/mm/mmu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 9d4da6ac28eb..4223d086aa17 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -420,6 +420,10 @@ static void __init build_mem_type_table(void) user_pgprot |= L_PTE_SHARED; kern_pgprot |= L_PTE_SHARED; vecs_pgprot |= L_PTE_SHARED; + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; + mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; + mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; #endif |