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| author | David S. Miller <davem@davemloft.net> | 2010-01-23 07:45:46 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-01-23 07:45:46 +0100 |
| commit | 6be325719b3e54624397e413efd4b33a997e55a3 (patch) | |
| tree | 57f321a56794cab2222e179b16731e0d76a4a68a /arch/arm/mm/proc-arm946.S | |
| parent | be2net: fix bug in rx page posting (diff) | |
| parent | Linux 2.6.33-rc5 (diff) | |
| download | linux-6be325719b3e54624397e413efd4b33a997e55a3.tar.xz linux-6be325719b3e54624397e413efd4b33a997e55a3.zip | |
Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Diffstat (limited to 'arch/arm/mm/proc-arm946.S')
| -rw-r--r-- | arch/arm/mm/proc-arm946.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 40c0449a139b..9a951239c86c 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -183,16 +183,17 @@ ENTRY(arm946_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size * (same as arm926) */ -ENTRY(arm946_flush_kern_dcache_page) - add r1, r0, #PAGE_SZ +ENTRY(arm946_flush_kern_dcache_area) + add r1, r0, r1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -280,7 +281,7 @@ ENTRY(arm946_cache_fns) .long arm946_flush_user_cache_range .long arm946_coherent_kern_range .long arm946_coherent_user_range - .long arm946_flush_kern_dcache_page + .long arm946_flush_kern_dcache_area .long arm946_dma_inv_range .long arm946_dma_clean_range .long arm946_dma_flush_range |