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authorCatalin Marinas <catalin.marinas@arm.com>2011-11-22 18:30:29 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2011-12-08 11:30:39 +0100
commit1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001 (patch)
treeb04e3b1fd23ba81a643f64cba113551d127111a0 /arch/arm/mm/proc-macros.S
parentARM: LPAE: Page table maintenance for the 3-level format (diff)
downloadlinux-1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001.tar.xz
linux-1b6ba46b7efa31055eb993a6f2c6bbcb8b35b001.zip
ARM: LPAE: MMU setup for the 3-level page table format
This patch adds the MMU initialisation for the LPAE page table format. The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new proc-v7-3level.S file contains the TTB initialisation, context switch and PTE setting code with the LPAE. The TTBRx split is based on the PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings (supersections) and a few other memory types in mmu.c are conditionally compiled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
-rw-r--r--arch/arm/mm/proc-macros.S5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 307a4def8d3a..2d8ff3ad86d3 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -91,8 +91,9 @@
#if L_PTE_SHARED != PTE_EXT_SHARED
#error PTE shared bit mismatch
#endif
-#if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
- L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
+#if !defined (CONFIG_ARM_LPAE) && \
+ (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
+ L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
#error Invalid Linux PTE bit settings
#endif
#endif /* CONFIG_MMU */