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authorWill Deacon <will.deacon@arm.com>2012-09-01 06:22:12 +0200
committerWill Deacon <will.deacon@arm.com>2012-11-09 15:13:20 +0100
commit26ffd0d43b186b0d5186354da8714a1c2d360df0 (patch)
tree405c83d298530b65bb64630da52cfb368927691a /arch/arm/mm/proc-macros.S
parentARM: mm: introduce L_PTE_VALID for page table entries (diff)
downloadlinux-26ffd0d43b186b0d5186354da8714a1c2d360df0.tar.xz
linux-26ffd0d43b186b0d5186354da8714a1c2d360df0.zip
ARM: mm: introduce present, faulting entries for PAGE_NONE
PROT_NONE mappings apply the page protection attributes defined by _P000 which translate to PAGE_NONE for ARM. These attributes specify an XN, RDONLY pte that is inaccessible to userspace. However, on kernels configured without support for domains, such a pte *is* accessible to the kernel and can be read via get_user, allowing tasks to read PROT_NONE pages via syscalls such as read/write over a pipe. This patch introduces a new software pte flag, L_PTE_NONE, that is set to identify faulting, present entries. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
-rw-r--r--arch/arm/mm/proc-macros.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b29a2265af01..eb6aa73bc8b7 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -167,6 +167,10 @@
tst r1, #L_PTE_YOUNG
tstne r1, #L_PTE_PRESENT
moveq r3, #0
+#ifndef CONFIG_CPU_USE_DOMAINS
+ tstne r1, #L_PTE_NONE
+ movne r3, #0
+#endif
str r3, [r0]
mcr p15, 0, r0, c7, c10, 1 @ flush_pte