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authorCatalin Marinas <catalin.marinas@arm.com>2010-12-07 16:56:29 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-13 00:25:58 +0100
commitda30e0ac0f9a521f0cfec8145ddd1ad131f66d61 (patch)
tree4a9002e6fca4d4763b40908403fc177153b9a6a8 /arch/arm/mm/proc-macros.S
parentARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7 (diff)
downloadlinux-da30e0ac0f9a521f0cfec8145ddd1ad131f66d61.tar.xz
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ARM: 6528/1: Use CTR for the I-cache line size on ARMv7
The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
-rw-r--r--arch/arm/mm/proc-macros.S10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 321555b894d1..b795afd0a2c6 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -72,6 +72,16 @@
mov \reg, \reg, lsl \tmp @ actual cache line size
.endm
+/*
+ * icache_line_size - get the minimum I-cache line size from the CTR register
+ * on ARMv7.
+ */
+ .macro icache_line_size, reg, tmp
+ mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
+ and \tmp, \tmp, #0xf @ cache line size encoding
+ mov \reg, #4 @ bytes per word
+ mov \reg, \reg, lsl \tmp @ actual cache line size
+ .endm
/*
* Sanity check the PTE configuration for the code below - which makes