diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-18 00:53:41 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-18 00:53:41 +0100 |
| commit | a695bc683609a2b815915e4cfcd93e4ccc0e2cae (patch) | |
| tree | 824d6b35783317f929fe13a9efcc8a35d5e00311 /arch/arm/mm/proc-mohawk.S | |
| parent | printk: fix new kernel-doc warnings (diff) | |
| parent | Merge branch 'cache' (early part) (diff) | |
| download | linux-a695bc683609a2b815915e4cfcd93e4ccc0e2cae.tar.xz linux-a695bc683609a2b815915e4cfcd93e4ccc0e2cae.zip | |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
PCMCIA: fix pxa2xx_lubbock modular build error
[ARM] Update mach-types
[ARM] pxa: fix no reference of cpu_is_pxa25x() in devices.c
[ARM] pxa/cm-x300: add PWM backlight support
revert "[ARM] pxa/cm-x300: add PWM backlight support"
ARM: use flush_kernel_dcache_area() for dmabounce
ARM: add size argument to __cpuc_flush_dcache_page
ARM: 5848/1: kill flush_ioremap_region()
ARM: cache-l2x0: make better use of background cache handling
ARM: cache-l2x0: avoid taking spinlock for every iteration
[ARM] Kirkwood: Add LaCie Network Space v2 support
ARM: dove: fix the mm mmu flags of the pj4 procinfo
Diffstat (limited to 'arch/arm/mm/proc-mohawk.S')
| -rw-r--r-- | arch/arm/mm/proc-mohawk.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index 52b5fd74fbb3..9674d36cc97d 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -186,15 +186,16 @@ ENTRY(mohawk_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(mohawk_flush_kern_dcache_page) - add r1, r0, #PAGE_SZ +ENTRY(mohawk_flush_kern_dcache_area) + add r1, r0, r1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -273,7 +274,7 @@ ENTRY(mohawk_cache_fns) .long mohawk_flush_user_cache_range .long mohawk_coherent_kern_range .long mohawk_coherent_user_range - .long mohawk_flush_kern_dcache_page + .long mohawk_flush_kern_dcache_area .long mohawk_dma_inv_range .long mohawk_dma_clean_range .long mohawk_dma_flush_range |