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authorJonathan Austin <Jonathan.Austin@arm.com>2014-01-13 12:10:57 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-02-10 12:48:00 +0100
commitddb2ff731b53ae28ec3a2af0da96a108b8bad814 (patch)
treec9cf3b1d6bbc4769893a0252c66f3aae3a71a3c6 /arch/arm/mm/proc-v7.S
parentLinux 3.14-rc2 (diff)
downloadlinux-ddb2ff731b53ae28ec3a2af0da96a108b8bad814.tar.xz
linux-ddb2ff731b53ae28ec3a2af0da96a108b8bad814.zip
ARM: 7940/1: add support for the Cortex-A12 processor
The A12 behaves as the A7/A15 does with respect to setting the SMP bit, and doesn't require TLB ops broadcasting to be explicitly enabled like the A9 does. Note that as the ACTLR cannot (usually) be written from non-secure, it is the responsibility of the bootloader/firmware to set this bit per core - it is done here in Linux as last resort in case of bad firmware. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r--arch/arm/mm/proc-v7.S11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index bd1781979a39..7f9de7e88cd3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -192,6 +192,7 @@ __v7_cr7mp_setup:
mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
b 1f
__v7_ca7mp_setup:
+__v7_ca12mp_setup:
__v7_ca15mp_setup:
mov r10, #0
1:
@@ -484,6 +485,16 @@ __v7_ca7mp_proc_info:
.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
/*
+ * ARM Ltd. Cortex A12 processor.
+ */
+ .type __v7_ca12mp_proc_info, #object
+__v7_ca12mp_proc_info:
+ .long 0x410fc0d0
+ .long 0xff0ffff0
+ __v7_proc __v7_ca12mp_setup
+ .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
+
+ /*
* ARM Ltd. Cortex A15 processor.
*/
.type __v7_ca15mp_proc_info, #object