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| author | Will Deacon <will.deacon@arm.com> | 2011-11-15 14:25:04 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2011-12-06 15:04:14 +0100 |
| commit | 1a4baafa7d203da1cceb302c2df38f0fea1c17a1 (patch) | |
| tree | f64d1b22be6f3255ccb73470a9799890972bd670 /arch/arm/mm/proc-xsc3.S | |
| parent | ARM: suspend: use idmap_pgd instead of suspend_pgd (diff) | |
| download | linux-1a4baafa7d203da1cceb302c2df38f0fea1c17a1.tar.xz linux-1a4baafa7d203da1cceb302c2df38f0fea1c17a1.zip | |
ARM: proc-*.S: place cpu_reset functions into .idmap.text section
The CPU reset functions disable the MMU and therefore must be executed
with an identity mapping in place.
This patch places the CPU reset functions into the .idmap.text section,
causing the idmap code to include them as part of the identity mapping.
Acked-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
| -rw-r--r-- | arch/arm/mm/proc-xsc3.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index abf0507a08ae..b0d57869da2d 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -105,6 +105,7 @@ ENTRY(cpu_xsc3_proc_fin) * loc: location to jump to for soft reset */ .align 5 + .pushsection .idmap.text, "ax" ENTRY(cpu_xsc3_reset) mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE msr cpsr_c, r1 @ reset CPSR @@ -119,6 +120,8 @@ ENTRY(cpu_xsc3_reset) @ already containing those two last instructions to survive. mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs mov pc, r0 +ENDPROC(cpu_xsc3_reset) + .popsection /* * cpu_xsc3_do_idle() |