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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-06-29 19:24:21 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-29 19:24:21 +0200 |
| commit | 8799ee9f49f6171fd58f4d64f8c067ca49006a5d (patch) | |
| tree | b746b8800bc99633f31505d151624c8ccd75cd47 /arch/arm/mm/proc-xsc3.S | |
| parent | [ARM] 3666/1: TRIZEPS4 [1/5] core (diff) | |
| download | linux-8799ee9f49f6171fd58f4d64f8c067ca49006a5d.tar.xz linux-8799ee9f49f6171fd58f4d64f8c067ca49006a5d.zip | |
[ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to". On others, this bit is required to
be one, and others it's required to be zero. Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.
With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
| -rw-r--r-- | arch/arm/mm/proc-xsc3.S | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 8d32e21fe151..9aea506d3e65 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -487,7 +487,14 @@ cpu_xsc3_name: __xsc3_proc_info: .long 0x69056000 .long 0xffffe000 - .long 0x00000c0e + .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ b __xsc3_setup .long cpu_arch_name .long cpu_elf_name |