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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-08 17:18:37 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-08 17:18:37 +0100 |
| commit | 0de9a00fd6e0a137c63fbbfb6012bf34cc0ab7c4 (patch) | |
| tree | bda182d9407e32354620e9188258c86cad2e3813 /arch/arm/mm | |
| parent | ARM: 5868/1: ARM: fix "BUG: using smp_processor_id() in preemptible code" (diff) | |
| parent | [ARM] pxa: fix strange characters in zaurus gpio .desc (diff) | |
| download | linux-0de9a00fd6e0a137c63fbbfb6012bf34cc0ab7c4.tar.xz linux-0de9a00fd6e0a137c63fbbfb6012bf34cc0ab7c4.zip | |
Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/cache-xsc3l2.c | 11 | ||||
| -rw-r--r-- | arch/arm/mm/proc-xsc3.S | 7 |
2 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 5d180cb0bd94..c3154928bccd 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c @@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void) if (!cpu_is_xsc3() || !xsc3_l2_present()) return 0; - if (!(get_cr() & CR_L2)) { + if (get_cr() & CR_L2) { pr_info("XScale3 L2 cache enabled.\n"); - adjust_cr(CR_L2, CR_L2); xsc3_l2_inv_all(); - } - outer_cache.inv_range = xsc3_l2_inv_range; - outer_cache.clean_range = xsc3_l2_clean_range; - outer_cache.flush_range = xsc3_l2_flush_range; + outer_cache.inv_range = xsc3_l2_inv_range; + outer_cache.clean_range = xsc3_l2_clean_range; + outer_cache.flush_range = xsc3_l2_flush_range; + } return 0; } diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 96456f548798..8e4f6dca8997 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -407,6 +407,13 @@ __xsc3_setup: adr r5, xsc3_crval ldmia r5, {r5, r6} + +#ifdef CONFIG_CACHE_XSC3L2 + mrc p15, 1, r0, c0, c0, 1 @ get L2 present information + ands r0, r0, #0xf8 + orrne r6, r6, #(1 << 26) @ enable L2 if present +#endif + mrc p15, 0, r0, c1, c0, 0 @ get control register bic r0, r0, r5 @ ..V. ..R. .... ..A. orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) |