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authorArnaud Patard (Rtp) <arnaud.patard@rtp-net.org>2010-12-20 16:48:57 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2011-01-03 10:20:23 +0100
commit8305ed75d1418f02933a48bcabdbb5032d885628 (patch)
tree2708abad21787d76a2ea838c56ddc9d167c4a7a6 /arch/arm/plat-mxc/ehci.c
parentarch/arm/plat-mxc/ehci.c: fix errors/typos (diff)
downloadlinux-8305ed75d1418f02933a48bcabdbb5032d885628.tar.xz
linux-8305ed75d1418f02933a48bcabdbb5032d885628.zip
MX51: Add support for usb host 2
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/ehci.c')
-rw-r--r--arch/arm/plat-mxc/ehci.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index a45660301b08..8772ce346a58 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -49,6 +49,7 @@
#define MXC_OTG_OFFSET 0
#define MXC_H1_OFFSET 0x200
+#define MXC_H2_OFFSET 0x400
/* USB_CTRL */
#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
@@ -61,6 +62,11 @@
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+
#define MXC_USBCMD_OFFSET 0x140
/* USBCMD */
@@ -266,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
case 1: /* Host 1 port */
usbotg_base = usb_base + MXC_H1_OFFSET;
break;
+ case 2: /* Host 2 port */
+ usbotg_base = usb_base + MXC_H2_OFFSET;
+ break;
default:
printk(KERN_ERR"%s no such port %d\n", __func__, port);
ret = -ENOENT;
@@ -329,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
break;
+ case 2: /* Host 2 ULPI */
+ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+ if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+ /* HOST1 wakeup/ULPI intr enable */
+ v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+ } else {
+ /* HOST1 wakeup/ULPI intr disable */
+ v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+ }
+
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+ else
+ v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+ __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+ break;
}
error: