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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-01-06 23:33:32 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-01-06 23:33:32 +0100
commit404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34 (patch)
tree99119edc53fdca73ed7586829b8ee736e09440b3 /arch/arm/plat-mxc/include/mach/mx35.h
parentMerge branch 'pgt' (early part) into devel (diff)
parentMerge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into dev... (diff)
downloadlinux-404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34.tar.xz
linux-404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34.zip
Merge branch 'devel-stable' into devel
Conflicts: arch/arm/mach-pxa/clock.c arch/arm/mach-pxa/clock.h
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx35.h')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h51
1 files changed, 14 insertions, 37 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6267cff6035d..d13dbfeef08a 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -11,7 +11,6 @@
#define MX35_L2CC_SIZE SZ_1M
#define MX35_AIPS1_BASE_ADDR 0x43f00000
-#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX35_AIPS1_SIZE SZ_1M
#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
@@ -33,7 +32,6 @@
#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
#define MX35_SPBA0_BASE_ADDR 0x50000000
-#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
#define MX35_SPBA0_SIZE SZ_1M
#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
@@ -44,7 +42,6 @@
#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
#define MX35_AIPS2_BASE_ADDR 0x53f00000
-#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX35_AIPS2_SIZE SZ_1M
#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
@@ -68,15 +65,19 @@
#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
-
-#define MX35_OTG_BASE_ADDR 0x53ff4000
+#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
+#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
+/*
+ * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
+ * HS. When host support was implemented only a preliminary document was
+ * available, which told 0x400. This works fine.
+ */
+#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
#define MX35_ROMP_BASE_ADDR 0x60000000
-#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
#define MX35_ROMP_SIZE SZ_1M
#define MX35_AVIC_BASE_ADDR 0x68000000
-#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX35_AVIC_SIZE SZ_1M
/*
@@ -92,18 +93,17 @@
#define MX35_CS3_BASE_ADDR 0xb2000000
#define MX35_CS4_BASE_ADDR 0xb4000000
-#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000
+#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
#define MX35_CS4_SIZE SZ_32M
#define MX35_CS5_BASE_ADDR 0xb6000000
-#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000
+#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
#define MX35_CS5_SIZE SZ_32M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define MX35_X_MEMC_BASE_ADDR 0xb8000000
-#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
#define MX35_X_MEMC_SIZE SZ_64K
#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
@@ -114,12 +114,8 @@
#define MX35_NFC_BASE_ADDR 0xbb000000
#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
-#define MX35_IO_ADDRESS(x) ( \
- IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \
- IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
- IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
- IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
- IMX_IO_ADDRESS(x, MX35_SPBA0))
+#define MX35_IO_P2V(x) IMX_IO_P2V(x)
+#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
/*
* Interrupt numbers
@@ -153,8 +149,8 @@
#define MX35_INT_UART2 32
#define MX35_INT_NFC 33
#define MX35_INT_SDMA 34
-#define MX35_INT_USBHS 35
-#define MX35_INT_USBOTG 37
+#define MX35_INT_USB_HS 35
+#define MX35_INT_USB_OTG 37
#define MX35_INT_MSHC1 39
#define MX35_INT_ESAI 40
#define MX35_INT_IPU_ERR 41
@@ -190,23 +186,4 @@
#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
-#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
-#define MX35_SYSTEM_REV_NUM 3
-
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
-#define MXC_INT_OWIRE MX35_INT_OWIRE
-#define MXC_INT_GPU2D MX35_INT_GPU2D
-#define MXC_INT_ASRC MX35_INT_ASRC
-#define MXC_INT_USBHS MX35_INT_USBHS
-#define MXC_INT_USBOTG MX35_INT_USBOTG
-#define MXC_INT_ESAI MX35_INT_ESAI
-#define MXC_INT_CAN1 MX35_INT_CAN1
-#define MXC_INT_CAN2 MX35_INT_CAN2
-#define MXC_INT_MLB MX35_INT_MLB
-#define MXC_INT_SPDIF MX35_INT_SPDIF
-#define MXC_INT_FEC MX35_INT_FEC
-#endif
-
#endif /* ifndef __MACH_MX35_H__ */