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| author | Paul Walmsley <paul@pwsan.com> | 2009-05-13 01:27:09 +0200 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-05-13 01:27:09 +0200 |
| commit | fa0406a8d8c3a4a302085ccd031d999161405f70 (patch) | |
| tree | bc37051ba47599b871a0f438070821f8c4bbf0ea /arch/arm/plat-mxc | |
| parent | OMAP3 clock: add interconnect barriers to CORE DPLL M2 change (diff) | |
| download | linux-fa0406a8d8c3a4a302085ccd031d999161405f70.tar.xz linux-fa0406a8d8c3a4a302085ccd031d999161405f70.zip | |
OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change
Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
mode. This prevents the SDRC from attempting to power off the SDRAM,
which can cause the system to hang.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-mxc')
0 files changed, 0 insertions, 0 deletions