diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2014-06-04 22:53:02 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-06-04 22:53:02 +0200 |
| commit | f8647b506d7116a1a3accd8d618184096e85f50b (patch) | |
| tree | f10bc7201fda2a36c035548a0ea62210ad57adb6 /arch/arm/plat-omap/dma.c | |
| parent | MIPS: IP22/IP28: Improve GIO support (diff) | |
| parent | MIPS: Call find_vma with the mmap_sem held (diff) | |
| download | linux-f8647b506d7116a1a3accd8d618184096e85f50b.tar.xz linux-f8647b506d7116a1a3accd8d618184096e85f50b.zip | |
Merge branch '3.15-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
| -rw-r--r-- | arch/arm/plat-omap/dma.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 5f5b975887fc..b5608b1f9fbd 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -70,6 +70,7 @@ static u32 errata; static struct omap_dma_global_context_registers { u32 dma_irqenable_l0; + u32 dma_irqenable_l1; u32 dma_ocp_sysconfig; u32 dma_gcr; } omap_dma_global_context; @@ -1973,10 +1974,17 @@ static struct irqaction omap24xx_dma_irq; /*----------------------------------------------------------------------------*/ +/* + * Note that we are currently using only IRQENABLE_L0 and L1. + * As the DSP may be using IRQENABLE_L2 and L3, let's not + * touch those for now. + */ void omap_dma_global_context_save(void) { omap_dma_global_context.dma_irqenable_l0 = p->dma_read(IRQENABLE_L0, 0); + omap_dma_global_context.dma_irqenable_l1 = + p->dma_read(IRQENABLE_L1, 0); omap_dma_global_context.dma_ocp_sysconfig = p->dma_read(OCP_SYSCONFIG, 0); omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); @@ -1991,6 +1999,8 @@ void omap_dma_global_context_restore(void) OCP_SYSCONFIG, 0); p->dma_write(omap_dma_global_context.dma_irqenable_l0, IRQENABLE_L0, 0); + p->dma_write(omap_dma_global_context.dma_irqenable_l1, + IRQENABLE_L1, 0); if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) p->dma_write(0x3 , IRQSTATUS_L0, 0); |