diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-21 17:52:18 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-21 17:52:18 +0100 |
| commit | b05005772f34497eb2b7415a651fe785cbe70e16 (patch) | |
| tree | b176aeb7fa9baf69e77ddd83e844727490bfcf28 /arch/arm26/kernel/fiq.c | |
| parent | V4L/DVB (3415): Msp3400-kthreads.c: make 3 functions static (diff) | |
| parent | Linux 2.6.16 (diff) | |
| download | linux-b05005772f34497eb2b7415a651fe785cbe70e16.tar.xz linux-b05005772f34497eb2b7415a651fe785cbe70e16.zip | |
Merge branch 'origin'
Conflicts:
Documentation/video4linux/CARDLIST.cx88
drivers/media/video/cx88/Kconfig
drivers/media/video/em28xx/em28xx-video.c
drivers/media/video/saa7134/saa7134-dvb.c
Resolved as in the original merge by Mauro Carvalho Chehab
Diffstat (limited to 'arch/arm26/kernel/fiq.c')
| -rw-r--r-- | arch/arm26/kernel/fiq.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm26/kernel/fiq.c b/arch/arm26/kernel/fiq.c index 08a97c9498ff..a24272b61f30 100644 --- a/arch/arm26/kernel/fiq.c +++ b/arch/arm26/kernel/fiq.c @@ -104,14 +104,14 @@ void set_fiq_regs(struct pt_regs *regs) { register unsigned long tmp, tmp2; __asm__ volatile ( - "mov %0, pc - bic %1, %0, #0x3 - orr %1, %1, %3 - teqp %1, #0 @ select FIQ mode - mov r0, r0 - ldmia %2, {r8 - r14} - teqp %0, #0 @ return to SVC mode - mov r0, r0" + "mov %0, pc \n" + "bic %1, %0, #0x3 \n" + "orr %1, %1, %3 \n" + "teqp %1, #0 @ select FIQ mode \n" + "mov r0, r0 \n" + "ldmia %2, {r8 - r14} \n" + "teqp %0, #0 @ return to SVC mode \n" + "mov r0, r0 " : "=&r" (tmp), "=&r" (tmp2) : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26) /* These registers aren't modified by the above code in a way @@ -125,14 +125,14 @@ void get_fiq_regs(struct pt_regs *regs) { register unsigned long tmp, tmp2; __asm__ volatile ( - "mov %0, pc - bic %1, %0, #0x3 - orr %1, %1, %3 - teqp %1, #0 @ select FIQ mode - mov r0, r0 - stmia %2, {r8 - r14} - teqp %0, #0 @ return to SVC mode - mov r0, r0" + "mov %0, pc \n" + "bic %1, %0, #0x3 \n" + "orr %1, %1, %3 \n" + "teqp %1, #0 @ select FIQ mode \n" + "mov r0, r0 \n" + "stmia %2, {r8 - r14} \n" + "teqp %0, #0 @ return to SVC mode \n" + "mov r0, r0 " : "=&r" (tmp), "=&r" (tmp2) : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26) /* These registers aren't modified by the above code in a way |